View STM32F417ZG_6955653.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this is information on a product in full production. june 2013 docid022063 rev 4 1/186 1 stm32f415xx stm32f417xx arm cortex-m4 32b mcu+fpu, 210dmi ps, up to 1mb flash/192+4kb ram, crypto, usb otg hs/fs, ethernet, 17 tims, 3 adcs, 15 comm. interfaces & camera datasheet - production data features ? core: arm 32-bit cortex?-m4 cpu with fpu, adaptive real-time accelerator (art accelerator?) allowing 0-wait state execution from flash memory, frequency up to 168 mhz, memory protection unit, 210 dmips/ 1.25 dmips/mhz (dhrystone 2.1), and dsp instructions ? memories ? up to 1 mbyte of flash memory ? up to 192+4 kbytes of sram including 64- kbyte of ccm (core coupled memory) data ram ? flexible static memory controller supporting compact flash, sram, psram, nor and nand memories ? lcd parallel interface, 8080/6800 modes ? clock, reset and supply management ? 1.8 v to 3.6 v applic ation supply and i/os ? por, pdr, pvd and bor ? 4-to-26 mhz crystal oscillator ? internal 16 mhz factory-trimmed rc (1% accuracy) ? 32 khz oscillator for rtc with calibration ? internal 32 khz rc with calibration ? low power ? sleep, stop and standby modes ?v bat supply for rtc, 2032 bit backup registers + optional 4 kb backup sram ? 312-bit, 2.4 msps a/d co nverters: up to 24 channels and 7.2 msps in triple interleaved mode ? 212-bit d/a converters ? general-purpose dma: 16-stream dma controller with fifos and burst support ? up to 17 timers: up to twelve 16-bit and two 32- bit timers up to 168 mhz, each with up to 4 ic/oc/pwm or pulse counter and quadrature (incremental) encoder input ? debug mode ? serial wire debug (swd) & jtag interfaces ? cortex-m4 embedded trace macrocell? ? up to 140 i/o ports with interrupt capability ? up to 136 fast i/os up to 84 mhz ? up to 138 5 v-tolerant i/os ? up to 15 communica tion interfaces ? up to 3 i 2 c interfaces (smbus/pmbus) ? up to 4 usarts/2 uarts (10.5 mbit/s, iso 7816 interface, lin, irda, modem control) ? up to 3 spis (42 mbits/s), 2 with muxed full-duplex i 2 s to achieve audio class accuracy via internal audio pll or external clock ? 2 can interfaces (2.0b active) ? sdio interface ? advanced connectivity ? usb 2.0 full-speed device/host/otg controller with on-chip phy ? usb 2.0 high-speed/full-speed device/host/otg controller with dedicated dma, on-chip full-speed phy and ulpi ? 10/100 ethernet mac with dedicated dma: supports ieee 1588v2 hardware, mii/rmii ? 8- to 14-bit parallel camera interface up to 54 mbytes/s ? cryptographic acceleration: hardware acceleration for aes 128, 192, 256, triple des, hash (md5, sha-1), and hmac ? true random number generator ? crc calculation unit ? 96-bit unique id ? rtc: subsecond accuracy, hardware calendar lqfp64 (10 10 mm) lqfp100 (14 14 mm) lqfp144 (20 20 mm) fbga ufbga176 (10 10 mm) lqfp176 (24 24 mm) wlcsp90 table 1. device summary reference part number stm32f415xx stm32f415rg, stm32f415vg, stm32f415zg, stm32f415og stm32f417xx stm32f417vg, stm32f417ig, STM32F417ZG, stm32f417ve, stm32f417ze, stm32f417ie www.st.com
contents stm32f415xx, stm32f417xx 2/186 docid022063 rev 4 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.1 arm ? cortex?-m4f core with embedded fl ash and sram . . . . . . . . 19 2.2.2 adaptive real-time memory accelerato r (art accelerator?) . . . . . . . . 19 2.2.3 memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.4 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.5 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 20 2.2.6 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.7 multi-ahb bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.8 dma controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.9 flexible static memory controller (fsmc) . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.10 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 22 2.2.11 external interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.12 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.13 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.14 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.15 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.16 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.17 regulator on/off and in ternal reset on/off availability . . . . . . . . . . 29 2.2.18 real-time clock (rtc), backup sram and backup registers . . . . . . . . 29 2.2.19 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.20 v bat operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.21 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.22 inter-integrated circuit interface (i2c) . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.23 universal synchronous/asynchronous receiver transmitters (usart) . 33 2.2.24 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.25 inter-integrated sound (i2s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.26 audio pll (plli2s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.27 secure digital input/output interface (sdi o) . . . . . . . . . . . . . . . . . . . . . 35 2.2.28 ethernet mac interface with dedi cated dma and ieee 1588 support . 35 2.2.29 controller area network (bxcan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
docid022063 rev 4 3/186 stm32f415xx, stm32f417xx contents 2.2.30 universal serial bus on-the-go full-spee d (otg_fs) . . . . . . . . . . . . . . . 36 2.2.31 universal serial bus on-the-go high-speed (otg_hs) . . . . . . . . . . . . . 36 2.2.32 digital camera interface (dcmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.33 cryptographic acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.34 random number generator (rng) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.35 general-purpose input/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.36 analog-to-digital converters (adcs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.37 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.38 digital-to-analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.39 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.40 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.3.2 vcap_1/vcap_2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.3.3 operating conditions at power-up / power-down (regulator on) . . . . . . 81 5.3.4 operating conditions at power-up / power-down (regulator off) . . . . . 81 5.3.5 embedded reset and power control bloc k characteristics . . . . . . . . . . . 81 5.3.6 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.3.7 wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.3.8 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.3.9 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.3.10 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
contents stm32f415xx, stm32f417xx 4/186 docid022063 rev 4 5.3.11 pll spread spectrum clock generatio n (sscg) characteristics . . . . . 103 5.3.12 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.3.13 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.3.14 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 109 5.3.15 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.3.16 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.3.17 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.3.18 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 5.3.19 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5.3.20 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5.3.21 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.3.22 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.3.23 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 5.3.24 dac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 5.3.25 fsmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 5.3.26 camera interface (dcmi) timing specifications . . . . . . . . . . . . . . . . . . 156 5.3.27 sd/sdio mmc card host interface (sdio) characteristics . . . . . . . . . 157 5.3.28 rtc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 6.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 6.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 appendix a application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 a.1 usb otg full speed (fs) interface solutions . . . . . . . . . . . . . . . . . . . . . 172 a.2 usb otg high speed (hs) interface solutions . . . . . . . . . . . . . . . . . . . . 174 a.3 ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
docid022063 rev 4 5/186 stm32f415xx, stm32f417xx list of tables list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f415xx and stm32f417xx: features and peripheral counts. . . . . . . . . . . . . . . . . . 13 table 3. regulator on/off and internal reset on/off availability. . . . . . . . . . . . . . . . . . . . . . . . . 29 table 4. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5. usart feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 6. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 7. stm32f41x pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 8. fsmc pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 9. alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 10. stm32f41x register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 11. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 12. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 13. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 14. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 15. limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 80 table 16. vcap_1/vcap_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 17. operating conditions at power-up / power-down (r egulator on) . . . . . . . . . . . . . . . . . . . . 81 table 18. operating conditions at power-up / power-down (r egulator off). . . . . . . . . . . . . . . . . . . . 81 table 19. embedded reset and power control block characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 20. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator enabl ed) or ram . . . . . . . . . . . . . . . . . . . 84 table 21. typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 22. typical and maximum current consumption in sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 88 table 23. typical and maximum current consumptions in st op mode . . . . . . . . . . . . . . . . . . . . . . . . 89 table 24. typical and maximum current consumptions in standby mode . . . . . . . . . . . . . . . . . . . . . 89 table 25. typical and maximum current consumptions in v bat mode. . . . . . . . . . . . . . . . . . . . . . . . 90 table 26. switching output i/o current cons umption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 27. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 28. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 29. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 30. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 31. hse 4-26 mhz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 table 32. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 33. hsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 34. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 35. main pll characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 36. plli2s (audio pll) characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 02 table 37. sscg parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 38. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 39. flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 40. flash memory programming with v pp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 41. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 42. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 43. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 44. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 9 table 45. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 46. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
list of tables stm32f415xx, stm32f417xx 6/186 docid022063 rev 4 table 47. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 48. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 49. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 50. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 51. characteristics of timx connected to the apb1 domain . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 52. characteristics of timx connected to the apb2 domain . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 53. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 54. scl frequency (f pclk1 = 42 mhz.,v dd = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 55. spi dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 56. i2s dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 57. usb otg fs startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 58. usb otg fs dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 59. usb otg fs electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 60. usb hs dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 table 61. usb hs clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 table 62. ulpi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 63. ethernet dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 64. dynamic characteristics: ehternet mac signals fo r smi. . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 65. dynamic characteristics: ethernet mac signals fo r rmii . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 66. dynamic characteristics: ethernet mac signals for mii . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 67. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 68. adc accuracy at f adc = 30 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 69. temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 table 70. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 71. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 72. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 73. internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 74. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 75. asynchronous non-multiplexed sram/psram/nor read timings . . . . . . . . . . . . . . . . . 139 table 76. asynchronous non-multiplexed sram/psram/nor write timings . . . . . . . . . . . . . . . . . 140 table 77. asynchronous multiplexed psram/nor read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 78. asynchronous multiplexed psram/nor write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 79. synchronous multiplexed nor/ psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 80. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 81. synchronous non-multiplexed nor/psram read ti mings . . . . . . . . . . . . . . . . . . . . . . . . 146 table 82. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 83. switching characteristics for pc card/cf read and write cycles in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 84. switching characteristics for pc card/cf read and write cycles in i/o space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 85. switching characteristics for nand flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 86. switching characteristics for na nd flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 87. dcmi characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 88. dynamic characteristics: sd / mmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 89. rtc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 90. wlcsp90 - 0.400 mm pitch wafer level chip size package mechanical data . . . . . . . . . 160 table 91. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 161 table 92. lqpf100 ? 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 163 table 93. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 165 table 94. ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 95. lqfp176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data . . . . . . . 168
docid022063 rev 4 7/186 stm32f415xx, stm32f417xx list of tables table 96. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 97. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 98. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
list of figures stm32f415xx, stm32f417xx 8/186 docid022063 rev 4 list of figures figure 1. compatible board design between stm32f 10xx/stm32f4xx for lqfp64 . . . . . . . . . . . . 15 figure 2. compatible board design stm32f10xx/stm32f2xx/stm32f4xx for lqfp100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 3. compatible board design between stm32f10xx/stm32f2xx/stm32f4xx for lqfp144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 4. compatible board design between stm32f2xx and stm32f4xx for lqfp176 and bga176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. stm32f41x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6. multi-ahb matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 7. power supply supervisor interconnection with in ternal reset off . . . . . . . . . . . . . . . . . . . 24 figure 8. pdr_on and nrst control with internal reset off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 9. regulator off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 10. startup in re gulator off mode: slow v dd slope - power-down reset risen after v cap_1 /v cap_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 11. startup in re gulator off mode: fast v dd slope - power-down reset risen before v cap_1 /v cap_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 28 figure 12. stm32f41x lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 13. stm32f41x lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 14. stm32f41x lqfp144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 15. stm32f41x lqfp176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 16. stm32f41x ufbga176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 figure 17. stm32f41x wlcsp90 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 18. stm32f41x memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 19. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 20. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 21. power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 22. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 23. external capacitor c ext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 24. typical current consumption versus temperature, run mode, code with data processing running from flash (art accelerato r on) or ram, and peripherals off . . . . 86 figure 25. typical current consumption versus temperature, run mode, code with data processing running from flash (art accelerato r on) or ram, and peripherals on . . . . . 86 figure 26. typical current consumption versus temperature, run mode, code with data processing running from flash (art accelerator off) or ram, and peripherals off . . . 87 figure 27. typical current consumption versus temperature, run mode, code with data processing running from flash (art accelerator off) or ram, and peripherals on . . . . 87 figure 28. typical v bat current consumption (lse and rtc on/backup ram off) . . . . . . . . . . . . 90 figure 29. typical v bat current consumption (lse and rtc on/backup ram on) . . . . . . . . . . . . . 91 figure 30. high-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 31. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 32. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 33. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 34. acc lsi versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 35. pll output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 36. pll output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 37. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 38. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 39. i 2 c bus ac waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
docid022063 rev 4 9/186 stm32f415xx, stm32f417xx list of figures figure 40. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 41. spi timing diagram - slave mode and cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 42. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 22 figure 43. i2s slave timing diagram (philip s protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 figure 44. i2s master timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 45. usb otg fs timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 125 figure 46. ulpi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 47. ethernet smi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 48. ethernet rmii timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 49. ethernet mii timing di agram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 50. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 figure 51. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 52. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . 134 figure 53. power supply and reference decoupling (v ref+ connected to v dda ). . . . . . . . . . . . . . . . 134 figure 54. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 55. asynchronous non-multip lexed sram/psram/nor read waveforms . . . . . . . . . . . . . . 139 figure 56. asynchronous non-multip lexed sram/psram/nor write wavefo rms . . . . . . . . . . . . . . 140 figure 57. asynchronous multiplexed psram/nor read wavefo rms. . . . . . . . . . . . . . . . . . . . . . . . 141 figure 58. asynchronous multiplexed psram/nor write wave forms . . . . . . . . . . . . . . . . . . . . . . . 142 figure 59. synchronous multiplexed nor/ psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 60. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 figure 61. synchronous non-multiplexed nor/psram read ti mings . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 62. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 figure 63. pc card/compactflash controller waveforms for common me mory read access . . . . . . 149 figure 64. pc card/compactflash controller waveforms for common me mory write access . . . . . . 149 figure 65. pc card/compactflash controlle r waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 figure 66. pc card/compactflash controlle r waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 figure 67. pc card/compactflash cont roller waveforms for i/o space read access . . . . . . . . . . . . 151 figure 68. pc card/compactflash cont roller waveforms for i/o space write access . . . . . . . . . . . . 152 figure 69. nand controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 70. nand controller waveforms for wr ite access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 71. nand controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 155 figure 72. nand controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 155 figure 73. dcmi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 figure 74. sdio high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 figure 75. sd default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 76. wlcsp90 - 0.400 mm pitch wafer level chip si ze package outline . . . . . . . . . . . . . . . . . 160 figure 77. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 161 figure 78. lqfp64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2 figure 79. lqfp100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 163 figure 80. lqfp100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 figure 81. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 165 figure 82. lqfp144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 83. ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 84. lqfp176 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 168 figure 85. lqfp176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 86. usb controller configured as peripheral-only and used in full speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 72 figure 87. usb controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 172
list of figures stm32f415xx, stm32f417xx 10/186 docid022063 rev 4 figure 88. usb controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 173 figure 89. usb controller configured as peripheral, host, or dual-mode and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 figure 90. mii mode using a 25 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 75 figure 91. rmii with a 50 mhz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 92. rmii with a 25 mhz crystal and phy with pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
docid022063 rev 4 11/186 stm32f415xx, stm32f417xx introduction 1 introduction this datasheet provides the description of the stm32f415xx and stm32f417xx lines of microcontrollers. for more details on the whole stmicroelectronics stm32? family, please refer to section 2.1: full compatibilit y throughout the family . the stm32f415xx and stm32f417xx datasheet should be read in conjunction with the stm32f4xx reference manual. the reference and flash programming manuals are both available from the stmicroelectronics website www.st.com . for information on the cortex?-m4 core, please refer to the cortex?-m4 programming manual (pm0214) available from www.st.com.
description stm32f415xx, stm32f417xx 12/186 docid022063 rev 4 2 description the stm32f415xx and stm32f417xx family is based on the high-performance arm ? cortex?-m4 32-bit risc core operating at a frequency of up to 168 mhz. the cortex-m4 core features a floating point unit (fpu) sing le precision which supports all arm single- precision data-processing instructions and data types. it also implements a full set of dsp instructions and a memory protection unit (m pu) which enhances application security. the cortex-m4 core with fpu will be referred to as cortex-m4f through out this document. the stm32f415xx and stm32f417xx family incorporates high-speed embedded memories (flash memory up to 1 mbyte, up to 192 kbytes of sram), up to 4 kbytes of backup sram, and an extensive range of enhanced i/os and peripherals connected to two apb buses, three ahb bu ses and a 32-bit mu lti-ahb bus matrix. all devices offer three 12-bit adcs, two dacs, a low-power rtc, twelve general-purpose 16-bit timers including two pwm timers for mo tor control, two general-purpose 32-bit timers. a true random number generator (rng), and a cryptographic acceleration cell. they also feature standard and advanced communication interfaces. ? up to three i 2 cs ? three spis, two i 2 ss full duplex. to achieve audio class accuracy, the i2s peripherals can be clocked via a dedicated internal audi o pll or via an external clock to allow synchronization. ? four usarts plus two uarts ? an usb otg full-spee d and a usb otg high- speed with full-speed capability (with the ulpi), ? two cans ? an sdio/mmc interface ? ethernet and the camera interface available on stm32f417xx devices only. new advanced peripherals include an sdio, an enhanced flexible static memory control (fsmc) interface (for devices offered in pa ckages of 100 pins and more), a camera interface for cmos sensors and a crypt ographic acceleration cell. refer to table 2: stm32f415xx and stm32f417xx: features and peripheral counts for the list of peripherals available on each part number. the stm32f415xx and stm32f417xx family operates in the ?40 to +105 c temperature range from a 1.8 to 3.6 v power supply. the supply voltage can drop to 1.7 v when the device operates in the 0 to 70 c temperat ure range using an external power supply supervisor: refer to section : internal reset off . a comprehensive set of power-saving mode allows the design of low-power applications. the stm32f415xx and stm32f417xx family offe rs devices in various packages ranging from 64 pins to 176 pins. the set of incl uded peripherals changes with the device chosen.
stm32f415xx, stm32f417xx description docid022063 rev 4 13/186 these features make the stm32f415xx and stm32f417xx microcontroller family suitable for a wide range of applications: ? motor drive and application control ? medical equipment ? industrial applications: plc, inverters, circuit breakers ? printers, and scanners ? alarm systems, video intercom, and hvac ? home audio appliances figure 5 shows the general block diagram of the device family. table 2. stm32f415xx and stm32f417xx: features and peripheral counts peripherals stm32f415rg stm32f415og stm32f415vg stm32f415zg stm32f417vx stm32f417zx stm32f417ix flash memory in kbytes 1024 512 1024 512 1024 512 1024 sram in kbytes system 192(112+16+64) backup 4 fsmc memory controller no yes (1) ethernet no yes timers general- purpose 10 advanced- control 2 basic 2 iwdg yes wwdg yes rtc yes random number generator yes
description stm32f415xx, stm32f417xx 14/186 docid022063 rev 4 communicatio n interfaces spi / i 2 s 3/2 (full duplex) (2) i 2 c 3 usart/uart 4/2 usb otg fs yes usb otg hs yes can 2 sdio yes camera interface no yes cryptography yes gpios 51 72 82 114 82 114 140 12-bit adc number of channels 3 16 13 16 24 16 24 24 12-bit dac number of channels yes 2 maximum cpu frequency 168 mhz operating voltage 1.8 to 3.6 v (3) operating temperatures ambient temperatures: ?40 to +85 c /?40 to +105 c junction temperature: ?40 to + 125 c package lqfp64 wlcsp90 lqfp100 lqfp144 lqfp100 lqfp144 ufbga176 lqfp176 1. for the lqfp100 and wlcsp90 packages, only fsmc bank1 or bank2 are available. bank1 can only support a multiplexed nor/psram memory using the ne1 chip select. bank2 can only support a 16- or 8-bi t nand flash memory using the nce2 chip select. the interrupt line cannot be used s ince port g is not available in this package. 2. the spi2 and spi3 interfaces give the flexibility to work in an exclusive way in either the spi mode or the i2s audio mode. 3. v dd /v dda minimum value of 1.7 v is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to section : internal reset off ). table 2. stm32f415xx and stm32f417xx: features and peripheral counts peripherals stm32f415rg stm32f415og stm32f415vg stm32f415zg stm32f417vx stm32f417zx stm32f417ix
docid022063 rev 4 15/186 stm32f415xx, stm32f417xx description 2.1 full compatibility throughout the family the stm32f415xx and stm32f417xx are part of the stm32f4 family. they are fully pin- to-pin, software and feature compatible with the stm32f2xx devices, allowing the user to try different memory densities, peripherals, and performances (fpu, higher frequency) for a greater degree of freedom during the development cycle. the stm32f415xx and stm32f 417xx devices maintain a close compatibility with the whole stm32f10xxx family. all functional pins are pin-to-pin compatible. the stm32f415xx and stm32f417xx, however, are not drop-in replacements for the stm32f10xxx devices: the two families do not have the same power scheme, and so their power pins are different. nonetheless, transi tion from the stm32f10xxx to the stm32f41x family remains simple as only a few pins are impacted. figure 4 , figure 3 , figure 2 , and figure 1 give compatible board designs between the stm32f41x, stm32f2xxx, and stm32f10xxx families. figure 1. compatible board design between stm32f10xx/stm32f4xx for lqfp64 31 116 17 32 33 48 64 49 47 v ss v ss v ss v ss 0 resistor or soldering bridge present for the stm32f10xx configuration, not present in the stm32f4xx configuration ai18489
description stm32f415xx, stm32f417xx 16/186 docid022063 rev 4 figure 2. compatible board design stm32f10xx/stm32f2xx/stm32f4xx for lqfp100 package figure 3. compatible board design between stm32f10xx/stm32f2xx/stm32f4xx for lqfp144 package 20 49 125 26 50 51 75 100 76 73 19 v ss v ss v dd v ss v ss v ss 0 resistor or soldering bridge present for the stm32f10xxx configuration, not present in the stm32f4xx configuration ai18488c 99 (v ss ) v ss v dd two 0 resistors connected to: - v ss for the stm32f10xx - v ss for the stm32f4xx v ss for stm32f10xx v dd for stm32f4xx - v ss , v dd or nc for the stm32f2xx ai18487d 31 71 136 37 72 73 108 144 109 v ss 0 resistor or soldering bridge present for the stm32f10xx configuration, not present in the stm32f4xx configuration 106 v ss 30 two 0 resistors connected to: - v ss for the stm32f10xx - v dd or signal from external power supply supervisor for the stm32f4xx v ss v dd v ss v ss 143 (pdr_on) v ss v dd v ss for stm32f10xx v dd for stm32f4xx - v ss , v dd or nc for the stm32f2xx signal from external power supply supervisor
docid022063 rev 4 17/186 stm32f415xx, stm32f417xx description figure 4. compatible board design between stm32f2xx and stm32f4xx for lqfp176 and bga176 packages ms19919v3 144 45 88 89 132 176 133 two 0 resistors connected to: - v ss , v dd or nc for the stm32f2xx - v dd or signal from external power supply supervisor for the stm32f4xx 171 (pdr_on) v ss v dd signal from external power supply supervisor
description stm32f415xx, stm32f417xx 18/186 docid022063 rev 4 2.2 device overview figure 5. stm32f41x block diagram 1. the timers connected to apb2 are clocked from ti mxclk up to 168 mhz, while the timers connected to apb1 are clocked from timxclk either up to 84 mhz or 168 mhz, depending on timpre bit configuration ai18511d gpio port a ahb/apb2 140 af pa[15:0] tim1 / pwm 4 compl. channels (tim1_ch1[1:4]n, 4 channels (tim1_ch1[1:4]etr, bkin as af rx, tx, ck, cts, rts as af mosi, miso, sck, nss as af apb1 30mhz 8 analog inputs common to the 3 adcs vddref_adc mosi/sd, miso/sd_ext, sck/ck nss/ws, mck as af tx, rx dac1_out as af itf wwdg 4 kb bkpsram rtc_af1 osc32_in osc32_out vdda, vssa nrst 16b sdio / mmc d[7:0] cmd, ck as af vbat = 1.65 to 3.6 v dma2 scl, sda, smba as af jtag & sw arm cortex-m4 168 mhz nvic etm mpu traceclk traced[3:0] ethernet mac 10/100 dma/ fifo mii or rmii as af mdio as af usb otg hs dp, dm ulpi:ck, d[7:0], dir, stp, nxt id, vbus, sof dma2 8 streams fifo art accel/ cache sram 112 kb clk, ne [3:0], a[23:0], d[31:0], oen, wen, nbl[3:0], nl, nreg, nwait/iordy, cd intn, niis16 as af rng camera interface hsync, vsync puixclk, d[13:0] phy usb otg fs dp dm id, vbus, sof fifo ahb1 168 mhz phy fifo @v dda @v dda por/pdr bor supply supervision @v dda pvd int por reset xtal 32 khz man agt rtc rc hs fclk rc l s pwr interface iwdg @v bat awu reset & clock control p l l1&2 pclkx vdd = 1.8 to 3.6 v vss vcap1, vcpa2 voltage regulator 3.3 to 1.2 v vdd power managmt rtc_af1 backup register ahb bus-matrix 8s7m ls 2 channels as af dac1 dac2 flash up to 1 mb sram, psram, nor flash, pc card (ata), nand flash external memory controller (fsmc) tim6 tim7 tim2 tim3 tim4 tim5 tim12 tim13 tim14 usart2 usart3 uart4 uart5 sp3/i2s3 i2c1/smbus i2c2/smbus i2c3/smbus bxcan1 bxcan2 spi1 ext it. wkup d-bus fifo fpu apb142 mhz (max) sram 16 kb ccm data ram 64 kb ahb3 ahb2 168 mhz njtrst, jtdi, jtck/swclk jtdo/swd, jtdo i-bus s-bus dma/ fifo dma1 8 streams fifo pb[15:0] pc[15:0] pd[15:0] pe[15:0] pf[15:0] pg[15:0] ph[15:0] pi[11:0] gpio port b gpio port c gpio port d gpio port e gpio port f gpio port g gpio port h gpio port i tim8 / pwm 16b 4 compl. channels (tim1_ch1[1:4]n, 4 channels (tim1_ch1[1:4]etr, bkin as af 1 channel as af 1 channel as af rx, tx, ck, cts, rts as af 8 analog inputs common to the adc1 & 2 8 analog inputs for adc3 dac2_out as af 16b 16b scl, sda, smba as af scl, sda, smba as af mosi/sd, miso/sd_ext, sck/ck nss/ws, mck as af tx, rx rx, tx as af rx, tx as af rx, tx as af cts, rts as af rx, tx as af cts, rts as af 1 channel as af smcard irda smcard irda 16b 16b 16b 1 channel as af 2 channels as af 32b 16b 16b 32b 4 channels 4 channels, etr as af 4 channels, etr as af 4 channels, etr as af dma1 ahb/apb1 ls osc_in osc_out hclkx xtal osc 4- 16mhz fifo sp2/i2s2 niord, iowr, int[2:3] adc3 adc2 adc1 temperature sensor if tim9 16b tim10 16b tim11 16b smcard irda usart1 irda usart6 smcard apb2 84 mhz @v dd @v dd @v dda tdes, aes256 hash
docid022063 rev 4 19/186 stm32f415xx, stm32f417xx description in the rcc_dckcfgr register. 2. the camera interface and ethernet are available only on stm32f417xx devices. 2.2.1 arm ? cortex?-m4f core with embedded flash and sram the arm cortex-m4f processor is the latest generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. the arm cortex-m4f 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the processor supports a set of dsp instructions which allow efficient signal processing and complex algorithm execution. its single precision fpu (floating point unit ) speeds up software development by using metalanguage development tools, while avoiding saturation. the stm32f415xx and stm32f417xx family is compatible with all ar m tools and software. figure 5 shows the general block diagram of the stm32f41x family. note: cortex-m4f is binary compatible with cortex-m3. 2.2.2 adaptive real-time memory accelerator (art accelerator?) the art accelerator? is a memory accelerator which is optimized for stm32 industry- standard arm ? cortex?-m4f processors. it balances the inherent performance advantage of the arm cortex-m4f over flash memory technologies, which normally requires the processor to wait for the flash memory at higher frequencies. to release the processor full 210 dmips performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit flash memory. based on coremark benchmark, the performance achieved thanks to the art accele rator is equivalent to 0 wait state program execution from flash memory at a cpu frequency up to 168 mhz. 2.2.3 memory protection unit the memory protection unit (mpu) is used to manage the cpu accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. this memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. the protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. the mpu is especially helpful for applications wh ere some critical or ce rtified code has to be protected against the misbehavior of other ta sks. it is usually managed by an rtos (real- time operating system). if a prog ram accesses a memory location that is prohibited by the mpu, the rtos can detect it and take action. in an rtos environment, the kernel can dynamically update the mpu area setting, based on the process to be executed. the mpu is optional and can be bypassed for applications that do not need it.
description stm32f415xx, stm32f417xx 20/186 docid022063 rev 4 2.2.4 embedded flash memory the stm32f41x devices embed a flash memory of 512 kbytes or 1 mbytes available for storing programs and data. 2.2.5 crc (cyclic redundan cy check) calculation unit the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a fixed generator polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the c rc calculation unit help s compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 2.2.6 embedded sram all stm32f41x products embed: ? up to 192 kbytes of system sram includi ng 64 kbytes of ccm (core coupled memory) data ram ram memory is accessed (read/write) at cpu clock speed with 0 wait states. ? 4 kbytes of backup sram this area is accessible only from the cpu. its content is protected against possible unwanted write accesses, and is retained in standby or v bat mode. 2.2.7 multi-ahb bus matrix the 32-bit multi-ahb bu s matrix interconnects all the ma sters (cpu, dmas, ethernet, usb hs) and the slaves (flash me mory, ram, fsmc, ahb and apb peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.
docid022063 rev 4 21/186 stm32f415xx, stm32f417xx description figure 6. multi-ahb matrix 2.2.8 dma controller (dma) the devices feature two general-purpose dual-port dmas (dma1 and dma2) with 8 streams each. they are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripher al transfers. they fe ature dedicated fifos for apb/ahb peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (ahb/apb). the two dma controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. the two dma controllers also have a double buffering feature, which autom ates the use and switching of two memory buffers without requiring any special code. each stream is connected to dedicated hardware dma requests, with support for software trigger on each stream. configuration is made by software and transfer sizes between source and destination are independent. arm cortex-m4 gp dma1 gp dma2 mac ethernet usb otg hs bus matrix-s s0 s1 s2 s3 s4 s5 s6 s7 icode dcode accel flash memory sram1 112 kbyte sram2 16 kbyte ahb1 peripherals ahb2 fsmc static memctl m0 m1 m2 m3 m4 m5 m6 i-bus d-bus s-bus dma_pi dma_mem1 dma_mem2 dma_p2 ethernet_m usb_hs_m ai18490c ccm data ram 64-kbyte apb1 apb2 peripherals
description stm32f415xx, stm32f417xx 22/186 docid022063 rev 4 the dma can be used with the main peripherals: ? spi and i 2 s ? i 2 c ? usart ? general-purpose, basic and advanced-control timers timx ? dac ? sdio ? cryptographic acceleration ? camera interface (dcmi) ? adc. 2.2.9 flexible static memory controller (fsmc) the fsmc is embedded in the stm32f415xx and stm32f417xx family. it has four chip select outputs supporting the following mode s: pccard/compact flash, sram, psram, nor flash and nand flash. functionality overview: ? write fifo ? maximum fsmc_clk frequency for synchronous accesses is 60 mhz. lcd parallel interface the fsmc can be configured to interface seam lessly with most graphic lcd controllers. it supports the intel 8080 and motorola 6800 modes, and is flexible enough to adapt to specific lcd interfaces. this lcd parallel inte rface capability makes it easy to build cost- effective graphic applications using lcd modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 2.2.10 nested vectored in terrupt controller (nvic) the stm32f415xx and stm32f417xx embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 82 maskable interrupt channels plus the 16 interrupt lines of the cortex?-m4f. ? closely coupled nvic gives low-latency interrupt processing ? interrupt entry vector table address passed directly to the core ? allows early processing of interrupts ? processing of late arriving, higher-priority interrupts ? support tail chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimum interrupt latency. 2.2.11 external interrupt /event controller (exti) the external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. each line can be independently configured to select the trigger
docid022063 rev 4 23/186 stm32f415xx, stm32f417xx description event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal apb2 clock period. up to 140 gpios can be connected to the 16 external interrupt lines. 2.2.12 clocks and startup on reset the 16 mhz internal rc oscillator is selected as the default cpu clock. the 16 mhz internal rc oscillator is factory-tr immed to offer 1% accuracy over the full temperature range . the application can then select as system clo ck either the rc oscillator or an external 4-26 mhz clock source. this clock can be monitored for failure. if a failure is detected, the system automatically switches back to the internal rc oscillator and a software interrupt is generated (if enabled). this clock source is input to a pll thus allowing to increase the frequency up to 168 mhz. simila rly, full interrupt ma nagement of the pll clock entry is available when necessary (for ex ample if an indirectly us ed external oscillator fails). several prescalers allow the configuration of th e three ahb buses, the high-speed apb (apb2) and the low-speed apb (apb1) domains. the maximum frequency of the three ahb buses is 168 mhz while th e maximum frequency of the high-speed apb domains is 84 mhz. the maximum allowe d frequency of the low-sp eed apb domain is 42 mhz. the devices embed a dedicated pll (plli2s ) which allows to achieve audio class performance. in this case, the i 2 s master clock can generate all standard sampling frequencies from 8 khz to 192 khz. 2.2.13 boot modes at startup, boot pins are used to select one out of three boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1 (pa9/pa10), usart3 (pc10/pc 11 or pb10/pb11), can2 (pb5/pb13), usb otg fs in device mode (pa11/pa12) through dfu (device firmware upgrade). 2.2.14 power supply schemes ? v dd = 1.8 to 3.6 v: external power supply for i/os and the internal regulator (when enabled), provided externally through v dd pins. ? v ssa , v dda = 1.8 to 3.6 v: external analog power supplies for adc, dac, reset blocks, rcs and pll. v dda and v ssa must be connected to v dd and v ss , respectively. ? v bat = 1.65 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. refer to figure 21: power supply scheme for more details. note: v dd /v dda minimum value of 1.7 v is obtained when the device operates in reduced temperature range, and with the use of an ex ternal power supply supervisor (refer to section : internal reset off ). refer to table 2 in order to identify the packages supporting this option.
description stm32f415xx, stm32f417xx 24/186 docid022063 rev 4 2.2.15 power supply supervisor internal reset on on packages embedding the pdr_on pin, th e power supply supervisor is enabled by holding pdr_on high. on all other packag es, the power supply supervisor is always enabled. the device has an integrated power-on reset (por) / power-down reset (pdr) circuitry coupled with a brownout reset (bor) circuitry. at power-on, por/pdr is always active and ensures proper operation starting from 1.8 v. after the 1.8 v por threshold level is reached, the option byte loading process star ts, either to confirm or modify default bor threshold levels, or to disable bor permanently. three bor thresholds are available through option bytes. the device remains in reset mode when v dd is below a specified threshold, v por/pdr or v bor , without the need for an external reset circuit. the device also features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. internal reset off this feature is available only on packages featuring the pdr_on pin. the internal power-on reset (por) / power-down reset (pdr) circ uitry is disabled with the pdr_on pin. an external power supply supervisor should monitor v dd and should maintain the device in reset mode as long as v dd is below a specified threshold. pdr_on should be connected to this external power supply supervisor. refer to figure 7: power supply supervisor interconnection with internal reset off . figure 7. power supply supervisor interconnection with internal reset off 1. pdr = 1.7 v for reduce temperature range; pdr = 1.8 v for all temperature range. ms31383v3 nrst v dd pdr_on external v dd power supply supervisor ext. reset controller active when v dd < 1.7 v or 1.8 v (1) v dd application reset signal (optional)
docid022063 rev 4 25/186 stm32f415xx, stm32f417xx description the v dd specified threshold, below which the device must be maintained under reset, is 1.8 v (see figure 7 ). this supply voltage can drop to 1.7 v when the device operates in the 0 to 70 c temperature range. a comprehensive set of power-saving mode allows to design low-power applications. when the internal reset is off, the following integrated features are no more supported: ? the integrated power-on reset (por) / power-down reset (pdr) circuitry is disabled ? the brownout reset (bor) circuitry is disabled ? the embedded programmable voltage detector (pvd) is disabled ? v bat functionality is no more available and v bat pin should be connected to v dd all packages, except for the lqfp64 and lqfp 100, allow to disable the internal reset through the pdr_on signal. figure 8. pdr_on and nrst control with internal reset off 1. pdr = 1.7 v for reduce temperature range; pdr = 1.8 v for all temperature range. 2.2.16 voltage regulator the regulator has four operating modes: ? regulator on ? main regulator mode (mr) ? low power regulator (lpr) ? power-down ? regulator off regulator on on packages embedding the bypass_reg pin, the regulator is enabled by holding bypass_reg low. on all ot her packages, the regula tor is always enabled. ms19009v6 v dd time pdr = 1.7 v or 1.8 v (1) time nrst pdr_on pdr_on reset by other source than power supply supervisor
description stm32f415xx, stm32f417xx 26/186 docid022063 rev 4 there are three power modes configured by software when regulator is on: ? mr is used in the nominal regulation mode (with different voltage scaling in run) in main regulator mode (mr mode), different voltage scaling are provided to reach the best compromise between maximum frequ ency and dynamic power consumption. refer to table 14: general operating conditions . ? lpr is used in the stop modes the lp regulator mode is configured by software when entering stop mode. ? power-down is used in standby mode. the power-down mode is activated only when entering in standby mode. the regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. the contents of th e registers and sram are lost) two external ceramic capacitors should be connected on v cap_1 & v cap_2 pin. refer to figure 21: power supply scheme and figure 16: vcap_1/vcap_2 operating conditions . all packages have regulator on feature. regulator off this feature is availa ble only on packages featuring the bypass_reg pin. the regulator is disabled by holding bypass_reg high. the regulator off mode allows to supply externally a v 12 voltage source through v cap_1 and v cap_2 pins. since the internal voltage scaling is not manage internally, the external voltage value must be aligned with the targetted maximum frequency. refer to table 14: general operating conditions . the two 2.2 f ceramic capacitors should be replaced by two 100 nf decoupling capacitors. refer to figure 21: power supply scheme when the regulator is off, there is no more internal monitoring on v 12 . an external power supply supervisor should be used to monitor the v 12 of the logic power domain. pa0 pin should be used for this purpose, and act as power-on reset on v 12 power domain. in regulator off mode the following features are no more supported: ? pa0 cannot be used as a gpio pin sinc e it allows to reset a part of the v 12 logic power domain which is not reset by the nrst pin. ? as long as pa0 is kept low, the debug mode cannot be used under power-on reset. as a consequence, pa0 and nrst pins must be managed separately if the debug connection under reset or pre-reset is required.
docid022063 rev 4 27/186 stm32f415xx, stm32f417xx description figure 9. regulator off the following conditions must be respected: ? v dd should always be higher than v cap_1 and v cap_2 to avoid current injection between power domains. ? if the time for v cap_1 and v cap_2 to reach v 12 minimum value is faster than the time for v dd to reach 1.8 v, then pa0 should be kept low to cover both conditions: until v cap_1 and v cap_2 reach v 12 minimum value and until v dd reaches 1.8 v (see figure 10 ). ? otherwise, if the time for v cap_1 and v cap_2 to reach v 12 minimum value is slower than the time for v dd to reach 1.8 v, then pa0 could be asserted low externally (see figure 11 ). ? if v cap_1 and v cap_2 go below v 12 minimum value and v dd is higher than 1.8 v, then a reset must be asserted on pa0 pin. note: the minimum value of v 12 depends on the maximum frequency targeted in the application (see table 14: general operating conditions ). ai18498v4 external v cap_1/2 power supply supervisor ext. reset controller active when v cap_1/2 < min v 12 v 12 v cap_1 v cap_2 bypass_reg v dd pa0 nrst application reset signal (optional) v dd v 12
description stm32f415xx, stm32f417xx 28/186 docid022063 rev 4 figure 10. startup in regulator off mode: slow v dd slope - power-down reset risen after v cap_1 /v cap_2 stabilization 1. this figure is valid both whatever the internal reset mode (onon or offoff). 2. pdr = 1.7 v for reduced temperature range; pdr = 1.8 v for all temperature ranges. figure 11. startup in regulator off mode: fast v dd slope - power-down reset risen before v cap_1 /v cap_2 stabilization 1. this figure is valid both whatever the internal reset mode (onon or offoff). 2. pdr = 1.7 v for a reduced temperature range; pdr = 1.8 v for all temperature ranges. ai18491e v dd time min v 12 pdr = 1.7 v or 1.8 v (2) v cap_1 /v cap_2 v 12 nrst time v dd time min v 12 v cap_1 /v cap_2 v 12 pa0 asserted externally nrst time ai18492d pdr = 1.7 v or 1.8 v (2)
docid022063 rev 4 29/186 stm32f415xx, stm32f417xx description 2.2.17 regulator on/off and in ternal reset on/off availability 2.2.18 real-time clock (rtc), backup sram and backup registers the backup domain of the stm32f415xx and stm32f417xx includes: ? the real-time clock (rtc) ? 4 kbytes of backup sram ? 20 backup registers the real-time clock (rtc) is an independent bc d timer/counter. dedica ted registers contain the second, minute, hour (in 12/24 hour), we ek day, date, month, year, in bcd (binary- coded decimal) format. correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. the rtc provides a programmable alarm and programmable periodic interrupts with wakeup from stop and standby modes. the sub-seconds value is also available in binary format. it is clocked by a 32.768 khz external crystal, resonator or oscillator, the internal low-power rc oscillator or the high -speed external clock divided by 128. the internal low-speed rc has a typical frequency of 32 khz. the rtc can be calibrated using an external 512 hz output to compensa te for any natural quartz deviation. two alarm registers are used to generate an alar m at a specific time and calendar fields can be independently masked for alarm comparison. to generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 s to every 36 hours. a 20-bit prescaler is used for the time base cl ock. it is by default configured to generate a time base of 1 second from a clock at 32.768 khz. the 4-kbyte backup sram is an eeprom-like memory area. it can be used to store data which need to be retained in v bat and standby mode. this memory area is disabled by default to minimize power consumption (see section 2.2.19: low-power modes ). it can be enabled by software. the backup registers are 32-bit registers used to store 80 bytes of user application data when v dd power is not present. backup registers are not reset by a system, a power reset, or when the device wakes up from the standby mode (see section 2.2.19: low-power modes ). additional 32-bit registers contain the prog rammable alarm subseconds, seconds, minutes, hours, day, and date. table 3. regulator on/off and in ternal reset on/off availability regulator on regulator off internal reset on internal reset off lqfp64 lqfp100 yes no yes no lqfp144 lqfp176 yes pdr_on set to v dd yes pdr_on connected to an external power supply supervisor wlcsp90 ufbga176 yes bypass_reg set to v ss yes bypass_reg set to v dd
description stm32f415xx, stm32f417xx 30/186 docid022063 rev 4 like backup sram, the rtc and backup registers are supplied through a switch that is powered either from the v dd supply when present or from the v bat pin. 2.2.19 low-power modes the stm32f415xx and stm32f417xx support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode the stop mode achieves the lowest power consumption while retaining the contents of sram and registers. all clocks in the v 12 domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled . the voltage regulator can also be put either in normal or in low-power mode. the device can be woken up from the stop mo de by any of the exti line (the exti line source can be one of the 16 external lines , the pvd output, the rtc alarm / wakeup / tamper / time stamp events, the usb otg fs/hs wakeup or the ethernet wakeup). ? standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire v 12 domain is powered off. the pll, the hsi rc and the hse crystal oscillators are also switched off. after entering standby mode, the sram and register conten ts are lost except for registers in the backup domain and the backup sram when selected. the device exits the standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pin, or an rtc alarm / wakeup / tamper /time stamp event occurs. the standby mode is not supported when the embedded voltage regulator is bypassed and the v 12 domain is controlled by an external power. 2.2.20 v bat operation the v bat pin allows to power the device v bat domain from an external battery, an external supercapacitor, or from v dd when no external battery and an external supercapacitor are present. v bat operation is activated when v dd is not present. the v bat pin supplies the rtc, the backup registers and the backup sram. note: when the microcontroller is supplied from v bat , external interrupts and rtc alarm/events do not exit it from v bat operation. when pdr_on pin is not connected to v dd (internal reset off), the v bat functionality is no more available and v bat pin should be connected to v dd . 2.2.21 timers and watchdogs the stm32f415xx and stm32f417xx devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. all timer counters can be frozen in debug mode.
docid022063 rev 4 31/186 stm32f415xx, stm32f417xx description table 4 compares the features of the advanced-c ontrol, general-purpose and basic timers. advanced-control timers (tim1, tim8) the advanced-control timers (tim1, tim8) can be seen as three-phase pwm generators multiplexed on 6 channels. they have complementary pwm outputs with programmable inserted dead times. they can also be considered as complete general-purpose timers. their 4 independent channels can be used for: ? input capture ? output compare ? pwm generation (edge- or center-aligned modes) ? one-pulse mode output if configured as standard 16-bit timers, they ha ve the same features as the general-purpose timx timers. if configured as 16-bit pwm generators, they have full modulation capability (0- 100%). table 4. timer feature comparison timer type timer counter resolutio n counter type prescaler factor dma request generatio n capture/ compare channels complementar y output max interface clock (mhz) max timer clock (mhz) advanced -control tim1, tim8 16-bit up, down, up/dow n any integer between 1 and 65536 yes 4 yes 84 168 general purpose tim2, tim5 32-bit up, down, up/dow n any integer between 1 and 65536 yes 4 no 42 84 tim3, tim4 16-bit up, down, up/dow n any integer between 1 and 65536 yes 4 no 42 84 tim9 16-bit up any integer between 1 and 65536 no 2 no 84 168 tim10 , tim11 16-bit up any integer between 1 and 65536 no 1 no 84 168 tim12 16-bit up any integer between 1 and 65536 no 2 no 42 84 tim13 , tim14 16-bit up any integer between 1 and 65536 no 1 no 42 84 basic tim6, tim7 16-bit up any integer between 1 and 65536 yes 0 no 42 84
description stm32f415xx, stm32f417xx 32/186 docid022063 rev 4 the advanced-control timer can work togethe r with the timx timers via the timer link feature for synchronizat ion or event chaining. tim1 and tim8 support indepe ndent dma request generation. general-purpose timers (timx) there are ten synchronizable general-purpose timers embedded in the stm32f41x devices (see table 4 for differences). ? tim2, tim3, tim4, tim5 the stm32f41x include 4 full-featured g eneral-purpose timers: tim2, tim5, tim3, and tim4.the tim2 and tim5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. the tim3 and tim4 timers are based on a 16- bit auto-reload up/downcounter and a 16-bit prescaler. they all feature 4 independent channels for input capture/ou tput compare, pwm or one-pul se mode output. this gives up to 16 input capture/output comp are/pwms on the largest packages. the tim2, tim3, tim4, tim5 general-purpose timers can work together, or with the other general-purpose timers and the advanc ed-control timers tim1 and tim8 via the timer link feature for synchronization or event chaining. any of these general-purpose timers can be used to generate pwm outputs. tim2, tim3, tim4, tim5 all have indepen dent dma request generation. they are capable of handling quadrature (incremental ) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. ? tim9, tim10, tim11, ti m12, tim13, and tim14 these timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim10, tim11, tim13, and tim14 feature one independent channel, whereas tim9 and tim12 have two independent channels fo r input capture/output compare, pwm or one-pulse mode output. they can be synchronized with the tim2, tim3, tim4, tim5 full-featured general-purpose timers. they can also be used as simple time bases. basic timers tim6 and tim7 these timers are mainly used for dac trigger and waveform generation. they can also be used as a generic 16-bit time base. tim6 and tim7 support indepe ndent dma request generation. independent watchdog the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 32 khz internal rc and as it operates independently from the main clock, it can operate in stop and stan dby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. it is hardware- or software-configurable through the option bytes. window watchdog the window watchdog is based on a 7-bit downcounter that can be set as free-running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode.
docid022063 rev 4 33/186 stm32f415xx, stm32f417xx description systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. it features: ? a 24-bit downcounter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0 ? programmable clock source. 2.2.22 inter-integrated circuit interface (i2c) up to three i2c bus interfaces can operate in multimaster and slave modes. they can support the standard-mode (up to 100 khz) and fast-mode (up to 400 khz) . they support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). a hardware crc generation/verification is embedded. they can be served by dma and they support smbus 2.0/pmbus. 2.2.23 universal synchr onous/asynchronous receiver transmitters (usart) the stm32f415xx and stm32f417xx embed four universal synchronous/asynchronous receiver transmitters (usart1, usart2, usart3 and usart6) and two universal asynchronous receiver transmitters (uart4 and uart5). these six interfaces provide asynchronous communication, irda sir endec support, multiprocessor communication mode, single-wire half-duplex communication mode and have lin master/slave capability. the usart1 and u sart6 interfaces are able to communicate at speeds of up to 10.5 mbit/s. the other available interfaces communicate at up to 5.25 mbit/s. usart1, usart2, usart3 and usart6 also provide hardware management of the cts and rts signals, smart card mode (iso 7816 compliant) and spi-like communication capability. all interf aces can be served by the dma controller.
description stm32f415xx, stm32f417xx 34/186 docid022063 rev 4 2.2.24 serial peripheral interface (spi) the stm32f41x feature up to three spis in slave and master modes in full-duplex and simplex communication modes. spi1 can communicate at up to 42 mbits/s, spi2 and spi3 can communicate at up to 21 mbit/s. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification supports basic sd card/mmc modes. all spis can be served by the dma controller. the spi interface can be configured to operat e in ti mode for comm unications in master mode and slave mode. 2.2.25 inter-integrated sound (i 2 s) two standard i 2 s interfaces (multiplexed with spi2 and spi3) are available. they can be operated in master or slave mode, in full duplex and half-duplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. audio sampling frequencies from 8 khz up to 192 khz are supported. when either or both of the i 2 s interfaces is/are configured in master mo de, the master clock can be output to the external dac/codec at 256 ti mes the sampling frequency. all i 2 sx can be served by the dma controller. 2.2.26 audio pll (plli2s) the devices feature an additional dedicated pll for audio i 2 s application. it allows to achieve error-free i 2 s sampling clock accuracy withou t compromising on the cpu performance, while using usb peripherals. table 5. usart feature comparison usart name standard features modem (rts/ cts) lin spi master irda smartcard (iso 7816) max. baud rate in mbit/s (oversampling by 16) max. baud rate in mbit/s (oversampling by 8) apb mapping usart1 x x x x x x 5.25 10.5 apb2 (max. 84 mhz) usart2 x x x x x x 2.62 5.25 apb1 (max. 42 mhz) usart3 x x x x x x 2.62 5.25 apb1 (max. 42 mhz) uart4 x - x - x - 2.62 5.25 apb1 (max. 42 mhz) uart5 x - x - x - 2.62 5.25 apb1 (max. 42 mhz) usart6 x x x x x x 5.25 10.5 apb2 (max. 84 mhz)
docid022063 rev 4 35/186 stm32f415xx, stm32f417xx description the plli2s configuration can be modified to manage an i 2 s sample rate change without disabling the main pll (pll) used for cpu, usb and ethernet interfaces. the audio pll can be programmed with very low error to obtain sampling rates ranging from 8 khz to 192 khz. in addition to the audio pll, a master clock input pin can be used to synchronize the i 2 s flow with an external pll (or codec output). 2.2.27 secure digital in put/output interface (sdio) an sd/sdio/mmc host interface is availabl e, that supports multimediacard system specification version 4.2 in three different da tabus modes: 1-bit (default), 4-bit and 8-bit. the interface allows data transfer at up to 48 mhz, and is compliant with the sd memory card specification version 2.0. the sdio card specification version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. the current version supports only one sd/sdi o/mmc4.2 card at any one time and a stack of mmc4.1 or previous. in addition to sd/sdio/mmc, this interface is fully compliant with the ce-ata digital protocol rev1.1. 2.2.28 ethernet mac interface with dedicated dma and ieee 1588 support peripheral available only on the stm32f417xx devices. the stm32f417xx devices prov ide an ieee-802.3-20 02-compliant media access controller (mac) for ethernet lan communications through an industry-standard medium- independent interface (mii) or a reduced medium-independent interface (rmii). the stm32f417xx requires an external physical interface device (phy) to connect to the physical lan bus (twisted-pair, fiber, etc.). the phy is connected to the stm32f417xx mii port using 17 signals for mii or 9 signals for rmii, and can be clocked using the 25 mhz (mii) from the stm32f417xx. the stm32f417xx includes the following features: ? supports 10 and 100 mbit/s rates ? dedicated dma controller allowing high-speed transfers between the dedicated sram and the descriptors (see the stm32f40x reference manual for details) ? tagged mac frame support (vlan support) ? half-duplex (csma/cd) and full-duplex operation ? mac control sublayer (control frames) support ? 32-bit crc generation and removal ? several address filtering modes for physic al and multicast address (multicast and group addresses) ? 32-bit status code for each transmitted or received frame ? internal fifos to buffer transmit and receive frames. the transmit fifo and the receive fifo are both 2 kbytes. ? supports hardware ptp (precision time protocol) in accordance with ieee 1588 2008 (ptp v2) with the time stamp compar ator connected to the tim2 input ? triggers interrupt when system time becomes greater than target time
description stm32f415xx, stm32f417xx 36/186 docid022063 rev 4 2.2.29 controller area network (bxcan) the two cans are compliant with the 2.0a and b (a ctive) specifications with a bitrate up to 1 mbit/s. they can receive and transmit standard frames with 11-bit id entifiers as well as extended frames with 29-bit identifiers. each can has three transmit mailboxes, two receive fifos with 3 stages and 28 shared scalable filter banks (all of them can be used even if one can is used). 256 bytes of sram are allocated for each can. 2.2.30 universal se rial bus on-the-go full-speed (otg_fs) the stm32f415xx and stm32f417xx embed an usb otg full-speed device/host/otg peripheral with integrated transceivers. the usb otg fs peripheral is compliant with the usb 2.0 specification and with the otg 1.0 sp ecification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg full-speed controller requires a dedicated 48 mhz clock that is generated by a pll connected to the hse oscillator. the major features are: ? combined rx and tx fifo size of 320 35 bits with dynamic fifo sizing ? supports the session request protocol (srp) and host negotiation protocol (hnp) ? 4 bidirectional endpoints ? 8 host channels with periodic out support ? hnp/snp/ip inside (no need for any external resistor) ? for otg/host modes, a power switch is needed in case bus-powered devices are connected 2.2.31 universal se rial bus on-the-go high-speed (otg_hs) the stm32f415xx and stm32f417xx devices embed a usb otg high-speed (up to 480 mb/s) device/host/otg peripheral. the usb otg hs supports both full-speed and high-speed operations. it integrates the transc eivers for full-speed operation (12 mb/s) and features a utmi low-pin interf ace (ulpi) for high-speed oper ation (480 mb/s). when using the usb otg hs in hs mode, an external ph y device connected to the ulpi is required. the usb otg hs peripheral is compliant wit h the usb 2.0 specification and with the otg 1.0 specification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg full-speed controller requires a dedicated 48 mhz clock that is generated by a pll co nnected to the hse oscillator. the major features are: ? combined rx and tx fifo size of 1 kbit 35 with dynamic fifo sizing ? supports the session request protocol (srp) and host negotiation protocol (hnp) ? 6 bidirectional endpoints ? 12 host channels with periodic out support ? internal fs otg phy support ? external hs or hs otg operation suppor ting ulpi in sdr mode. the otg phy is connected to the microcontroller ulpi port through 12 signals. it can be clocked using the 60 mhz output. ? internal usb dma ? hnp/snp/ip inside (no need for any external resistor) ? for otg/host modes, a power switch is needed in case bus-powered devices are connected
docid022063 rev 4 37/186 stm32f415xx, stm32f417xx description 2.2.32 digital cam era interface (dcmi) the camera interface is not available in stm32f415xx devices. stm32f417xx products embed a camera interface that can connect with camera modules and cmos sensors through an 8-bit to 14-bit parallel interface, to receive video data. the camera interface can sustain a data transfer ra te up to 54 mbyte/s at 54 mhz. it features: ? programmable polarity for the input pixel clock and synchronization signals ? parallel data communication can be 8-, 10-, 12- or 14-bit ? supports 8-bit progressive video monochrome or raw bayer format, ycbcr 4:2:2 progressive video, rgb 565 progressive video or compressed data (like jpeg) ? supports continuous mode or snapshot (a single frame) mode ? capability to automatically crop the image 2.2.33 cryptographic acceleration the stm32f415xx and stm32f417xx devices embed a cryptographic accelerator. this cryptographic accelerator provides a set of hardware acceleration for the advanced cryptographic algorithms usually needed to pr ovide confidentiality, authentication, data integrity and non repudiation when exchanging messages with a peer. these algorithms consists of: encryption/decryption ? des/tdes (data encryption standard/triple data encryption standard): ecb (electronic codebook) and cbc (cipher block chaining) chaining algorithms, 64-, 128- or 192-bit key ? aes (advanced encryption standard): ecb, cbc and ctr (counter mode) chaining algorithms, 128, 192 or 256-bit key universal hash ? sha-1 (secure hash algorithm) ?md5 ?hmac the cryptographic accelerator supports dma request generation. 2.2.34 random number generator (rng) all stm32f415xx and stm32f417xx products embed an rng that delivers 32-bit random numbers generated by an integrated analog circuit. 2.2.35 general-purpose input/outputs (gpios) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain, with or without pull-up or pull-down), as input (f loating, with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high-current -capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. the i/o configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the i/os registers. fast i/o handling a llowing maximum i/o toggling up to 84 mhz.
description stm32f415xx, stm32f417xx 38/186 docid022063 rev 4 2.2.36 analog-to-digital converters (adcs) three 12-bit analog-to-digital converters are embedded and each adc shares up to 16 external channels, performing conversions in the single-shot or scan mode. in scan mode, automatic conversion is performed on a selected group of analog inputs. additional logic functions embedded in the adc interface allow: ? simultaneous sample and hold ? interleaved sample and hold the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted vo ltage is outside the programmed thresholds. to synchronize a/d conversion and timers, t he adcs could be triggered by any of tim1, tim2, tim3, tim4, tim5, or tim8 timer. 2.2.37 temperature sensor the temperature sensor has to generate a voltage that varies linearly with temperature. the conversion range is between 1.8 v and 3.6 v. the temperature sensor is internally connected to the adc1_in16 input channel whic h is used to convert the sensor output voltage into a digital value. as the offset of the temperature sensor varies fr om chip to chip due to process variation, the internal temperature sensor is mainly suitab le for applications that detect temperature changes instead of absolute temperatures. if an accurate temperature reading is needed, then an external temperature sensor part should be used. 2.2.38 digital-to-analog converter (dac) the two 12-bit buffered dac channels can be used to convert two digital signals into two analog voltage signal outputs. this dual digital interface supports the following features: ? two dac converters: one for each output channel ? 8-bit or 12-bit monotonic output ? left or right data alignment in 12-bit mode ? synchronized update capability ? noise-wave generation ? triangular-wave generation ? dual dac channel independent or simultaneous conversions ? dma capability for each channel ? external triggers for conversion ? input voltage reference v ref+ eight dac trigger inputs are used in the device. the dac channels are triggered through the timer update outputs that are also connected to different dma streams. 2.2.39 serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target.
docid022063 rev 4 39/186 stm32f415xx, stm32f417xx description debug is performed using 2 pins only instead of 5 required by the jtag (jtag pins could be re-use as gpio with alternate function): the jtag tms and tck pins are shared with swdio and swclk, respectively, and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp. 2.2.40 embedded trace macrocell? the arm embedded trace macrocell provides a greater visibility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32f41x through a small number of etm pins to an external hardware trace port analyser (tpa) device. the tpa is connected to a host computer using usb, ethernet, or any other high-speed channel. real-time instru ction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. tpa hardware is commercially available from common development tool vendors. the embedded trace macrocell operates wi th third party debugger software tools.
pinouts and pin description stm32f415xx, stm32f417xx 40/186 docid022063 rev 4 3 pinouts and pin description figure 12. stm32f41x lqfp64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vbat pc14 pc15 nrst pc0 pc1 pc2 pc3 vssa vdda pa0_wkup pa1 pa2 vdd pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd2 pc12 pc11 pc10 pa15 pa14 vdd vcap_2 pa13 pa12 pa11 pa10 pa9 pa8 pc9 pc8 pc7 pc6 pb15 pb14 pb13 pb12 pa3 vss vdd pa4 pa5 pa6 pa7 pc4 pc5 pb0 pb1 pb2 pb10 pb11 vcap_1 vdd lqfp64 ai18493b pc13 ph0 ph1 vss
docid022063 rev 4 41/186 stm32f415xx, stm32f417xx pinouts and pin description figure 13. stm32f41x lqfp100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 pe2 pe3 pe4 pe5 pe6 vbat pc14 pc15 vss vdd ph0 nrst pc0 pc1 pc2 pc3 vdd vssa vref+ vdda pa0 pa1 pa2 vdd vss vcap_2 pa13 pa12 pa 11 pa10 pa9 pa8 pc9 pc8 pc7 pc6 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 pb15 pb14 pb13 pb12 pa3 vss vdd pa4 pa5 pa6 pa7 pc4 pc5 pb0 pb1 pb2 pe7 pe8 pe9 pe10 pe11 pe12 pe13 pe14 pe15 pb10 pb11 vcap_1 vdd vdd vss pe1 pe0 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pc12 pc11 pc10 pa15 pa14 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ai18495c lqfp100 pc13 ph1
pinouts and pin description stm32f415xx, stm32f417xx 42/186 docid022063 rev 4 figure 14. stm32f41x lqfp144 pinout v dd pdr_on pe1 pe0 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pg15 v dd v ss pg14 pg13 pg12 pg11 pg10 pg9 pd7 pd6 v dd v ss pd5 pd4 pd3 pd2 pd1 pd0 pc12 pc11 pc10 pa 15 pa 14 pe2 v dd pe3 v ss pe4 pe5 pa 13 pe6 pa 12 vbat pa 11 pc13 pa 10 pc14 pa 9 pc15 pa 8 pf0 pc9 pf1 pc8 pf2 pc7 pf3 pc6 pf4 v dd pf5 v ss v ss pg8 v dd pg7 pf6 pg6 pf7 pg5 pf8 pg4 pf9 pg3 pf10 pg2 ph0 pd15 ph1 pd14 nrst v dd pc0 v ss pc1 pd13 pc2 pd12 pc3 pd11 v ssa pd10 v dd pd9 v ref+ pd8 v dda pb15 pa 0 pb14 pa 1 pb13 pa 2 pb12 pa 3 v ss v dd pa 4 pa 5 pa 6 pa 7 pc4 pc5 pb0 pb1 pb2 pf11 pf12 v dd pf13 pf14 pf15 pg0 pg1 pe7 pe8 pe9 v ss v dd pe10 pe11 pe12 pe13 pe14 pe15 pb10 pb11 v cap_1 v dd 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 109 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 72 lqfp144 120 119 118 117 116 115 114 113 112 111 110 61 62 63 64 65 66 67 68 69 70 71 26 27 28 29 30 31 32 33 34 35 36 83 82 81 80 79 78 77 76 75 74 73 ai18496b v cap_2 v ss
docid022063 rev 4 43/186 stm32f415xx, stm32f417xx pinouts and pin description figure 15. stm32f41x lqfp176 pinout ms19916v3 pdr_on pe1 pe0 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pg15 pg14 pg13 pg12 pg11 pg10 pg9 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pc12 pc11 pc10 pi7 pi6 pe2 pe3 pe4 pe5 pa13 pe6 pa12 v bat pa11 pi8 pa10 pc14 pa9 pc15 pa8 pf0 pc9 pf1 pc8 pf2 pc7 pf3 pc6 pf4 pf5 pg8 pg7 pf6 pg6 pf7 pg5 pf8 pg4 pf9 pg3 pf10 pg2 ph0 pd15 ph1 pd14 nrst v pc0 v pc1 pd13 pc2 pd12 pc3 pd11 pd10 pd9 v ref+ pd8 pb15 pa0 pb14 pa1 pb13 pa2 pb12 pa3 pa4 pa5 pa6 pa7 pc4 pc5 pb0 pb1 pb2 pf11 pf12 v ss pf13 pf14 pf15 pg0 pg1 pe7 pe8 pe9 pe10 pe11 pe12 pe13 pe14 pe15 pb10 pb11 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 141 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 80 lqfp176 152 151 150 149 148 147 146 145 144 143 142 69 70 71 72 73 74 75 76 77 78 79 26 27 28 29 30 31 32 33 34 35 36 107 106 105 104 103 102 101 100 99 98 89 pi4 pa15 pa14 pi3 pi2 pi5 140 139 138 137 136 135 134 133 ph4 ph5 ph6 ph7 ph8 ph9 ph10 ph11 88 81 82 83 84 85 86 87 pi1 pi0 ph15 ph14 ph13 ph12 96 95 94 93 92 91 90 97 37 38 39 40 41 42 43 44 pc13 pi9 pi10 pi11 v ss ph2 ph3 v dd v ss v dd v dda v ssa v dda bypass_reg v dd v dd v ss v dd v cap_1 v dd v ss v dd v cap_2 v ss v dd v ss v dd v ss v dd v ss v dd v dd v ss v dd v ss v dd
pinouts and pin description stm32f415xx, stm32f417xx 44/186 docid022063 rev 4 figure 16. stm32f41x ufbga176 ballout 1. this figure shows the package top view. ai18497b 1 2 3 9 10 11 12 13 14 15 a pe3 pe2 pe1 pe0 pb8 pb5 pg14 pg13 pb4 pb3 pd7 pc12 pa15 pa14 pa13 b pe4 pe5 pe6 pb9 pb7 pb6 pg15pg12pg11pg10 pd6 pd0 pc11pc10pa12 cvbat pi7 pi6 pi5 pdr_on vdd vdd vdd vdd pg9 pd5 pd1 pi3 pi2 pa11 d pc13 pi8 pi9 pi4 boot0 vss vss vss pd4 pd3 pd2 ph15 pi1 pa10 e pc14 pf0 pi10 pi11 ph13 ph14 pi0 pa9 f pc15 vss vdd ph2 vss vss vss vss vss vss vcap_2 pc9 pa8 g ph0 vss vdd ph3 vss vss vss vss vss vss vdd pc8 pc7 h ph1 pf2 pf1 ph4 vss vss vss vss vss vss vdd pg8 pc6 j nrst pf3 pf4 ph5 vss vss vss vss vss vdd vdd pg7 pg6 kpf7 pf6 pf5 vdd vss vss vss vss vss ph12 pg5 pg4 pg3 lpf10 pf9 pf8 bypass_ reg ph11 ph10 pd15 pg2 m vssa pc0 pc1 pc2 pc3 pb2 pg1 vss vss vcap_1 ph6 ph8 ph9 pd14 pd13 nvref- pa1 pa0 pa4 pc4 pf13 pg0 vdd vdd vdd pe13 ph7 pd12 pd11 pd10 p vref+ pa2 pa6 pa5 pc5 pf12 pf15 pe8 pe9 pe11 pe14 pb12 pb13 pd9 pd8 r vdda pa3 pa7 pb1 pb0 pf11 pf14 pe7 pe10 pe12 pe15 pb10 pb11 pb14 pb15 vss 4 35678
docid022063 rev 4 45/186 stm32f415xx, stm32f417xx pinouts and pin description figure 17. stm32f41x wlcsp90 ballout 1. this figure shows the package bump view. a vbat pc13 pdr_on pb4 pd7 pd4 pc12 b pc15 vdd pb7 pb3 pd6 pd2 pa15 c pa0 vss pc11 pi0 pb6 pd5 pd1 d pc2 pb8 pa13 e pc3 vss f ph1 pa1 g nrst h vssa j pa2 pa4 pa7 pb2 pe11 pb11 pb12 ms30402v1 1 pa14 pi1 pa12 pa10 pa9 pc0 pc9 pc8 ph0 pb13 pc6 pd14 pd12 pe8 pe12 bypass_ reg pd9 pd8 pe9 pb14 2 3 4 5 6 7 8 9 10 vdd pc14 vcap_2 pa11 pb5 pd0 pc10 pa8 vss vdd vss vdd pc7 vdd pe10 pe14 vcap_1 pd15 pe13 pe15 pd10 pd11 pa3 pa6 pb1 pb10 pb15 pb9 boot0 vdda pb0 pe7 pa5 table 6. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o tta 3.3 v tolerant i/o directly connected to adc b dedicated boot0 pin rst bidirectional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabl ed through peripheral registers
pinouts and pin description stm32f415xx, stm32f417xx 46/186 docid022063 rev 4 table 7. stm32f41x pi n and ball definitions pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions a dditional functions lqfp64 wlcsp90 lqfp100 lqfp144 ufbga176 lqfp176 - - 1 1 a2 1 pe2 i/o ft traceclk/ fsmc_a23 / eth_mii_txd3 / eventout - - 2 2 a1 2 pe3 i/o ft traced0/fsmc_a19 / eventout - - 3 3 b1 3 pe4 i/o ft traced1/fsmc_a20 / dcmi_d4/ eventout - - 4 4 b2 4 pe5 i/o ft traced2 / fsmc_a21 / tim9_ch1 / dcmi_d6 / eventout - - 5 5 b3 5 pe6 i/o ft traced3 / fsmc_a22 / tim9_ch2 / dcmi_d7 / eventout 1a106 6 c1 6 v bat s - - - - d2 7 pi8 i/o ft (2)( 3) eventout rtc_tamp1, rtc_tamp2, rtc_ts 2a97 7 d1 8 pc13 i/oft (2) (3) eventout rtc_out, rtc_tamp1, rtc_ts 3b108 8 e1 9 pc14/osc32_in (pc14) i/o ft (2)( 3) eventout osc32_in (4) 4b99 9 f110 pc15/ osc32_out (pc15) i/o ft (2)( 3) eventout osc32_out (4) - - - - d3 11 pi9 i/o ft can1_rx / eventout - - - - e3 12 pi10 i/o ft eth_mii_rx_er / eventout - - - - e4 13 pi11 i/o ft otg_hs_ulpi_dir / eventout ----f214 v ss s ----f315 v dd s ---10e216 pf0 i/oft fsmc_a0 / i2c2_sda / eventout
docid022063 rev 4 47/186 stm32f415xx, stm32f417xx pinouts and pin description ---11h317 pf1 i/oft fsmc_a1 / i2c2_scl / eventout ---12h218 pf2 i/oft fsmc_a2 / i2c2_smba / eventout ---13j219 pf3 i/oft (4) fsmc_a3/eventout adc3_in9 ---14j320 pf4 i/oft (4) fsmc_a4/eventout adc3_in14 ---15k321 pf5 i/oft (4) fsmc_a5/eventout adc3_in15 -c91016g222 v ss s -b81117g323 v dd s ---18k224 pf6 i/oft (4) tim10_ch1 / fsmc_niord/ eventout adc3_in4 ---19k125 pf7 i/oft (4) tim11_ch1/fsmc_nreg / eventout adc3_in5 ---20l326 pf8 i/oft (4) tim13_ch1 / fsmc_niowr/ eventout adc3_in6 ---21l227 pf9 i/oft (4) tim14_ch1 / fsmc_cd/ eventout adc3_in7 - - - 22 l1 28 pf10 i/o ft (4) fsmc_intr/ eventout adc3_in8 5 f10 12 23 g1 29 ph0/osc_in (ph0) i/o ft eventout osc_in (4) 6f91324h130 ph1/osc_out (ph1) i/o ft eventout osc_out (4) 7 g10 14 25 j1 31 nrst i/o rs t 8 e10 15 26 m2 32 pc0 i/o ft (4) otg_hs_ulpi_stp/ eventout adc123_in10 9 - 16 27 m3 33 pc1 i/o ft (4) eth_mdc/ eventout adc123_in11 10 d10 17 28 m4 34 pc2 i/o ft (4) spi2_miso / otg_hs_ulpi_dir / eth_mii_txd2 /i2s2ext_sd/ eventout adc123_in12 table 7. stm32f41x pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions a dditional functions lqfp64 wlcsp90 lqfp100 lqfp144 ufbga176 lqfp176
pinouts and pin description stm32f415xx, stm32f417xx 48/186 docid022063 rev 4 11 e9 18 29 m5 35 pc3 i/o ft (4) spi2_mosi / i2s2_sd / otg_hs_ulpi_nxt / eth_mii_tx_clk / eventout adc123_in13 - - 19 30 g3 36 v dd s 12 h10 20 31 m1 37 v ssa s ----n1- v ref ? s - - 21 32 p1 38 v ref+ s 13 g9 22 33 r1 39 v dda s 14 c10 23 34 n3 40 pa0/wkup (pa0) i/o ft (5) usart2_cts/ uart4_tx/ eth_mii_crs / tim2_ch1_etr/ tim5_ch1 / tim8_etr/ eventout adc123_in0/wkup (4 ) 15 f8 24 35 n2 41 pa1 i/o ft (4) usart2_rts / uart4_rx/ eth_rmii_ref_clk / eth_mii_rx_clk / tim5_ch2 / tim2_ch2/ eventout adc123_in1 16 j10 25 36 p2 42 pa2 i/o ft (4) usart2_tx/tim5_ch3 / tim9_ch1 / tim2_ch3 / eth_mdio/ eventout adc123_in2 - - - - f4 43 ph2 i/o ft eth_mii_crs/eventou t - - - - g4 44 ph3 i/o ft eth_mii_col/eventou t ----h445 ph4 i/oft i2c2_scl / otg_hs_ulpi_nxt/ eventout - - - - j4 46 ph5 i/o ft i2c2_sda/ eventout table 7. stm32f41x pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions a dditional functions lqfp64 wlcsp90 lqfp100 lqfp144 ufbga176 lqfp176
docid022063 rev 4 49/186 stm32f415xx, stm32f417xx pinouts and pin description 17 h9 26 37 r2 47 pa3 i/o ft (4) usart2_rx/tim5_ch4 / tim9_ch2 / tim2_ch4 / otg_hs_ulpi_d0 / eth_mii_col/ eventout adc123_in3 18 e5 27 38 - - v ss s d9 l4 48 bypass_reg i ft 19 e4 28 39 k4 49 v dd s 20 j9 29 40 n4 50 pa4 i/o tta (4) spi1_nss / spi3_nss / usart2_ck / dcmi_hsync / otg_hs_sof/ i2s3_ws/ eventout adc12_in4 /dac_out1 21 g8 30 41 p4 51 pa5 i/o tta (4) spi1_sck/ otg_hs_ulpi_ck / tim2_ch1_etr/ tim8_ch1n/ eventout adc12_in5/dac_ou t2 22 h8 31 42 p3 52 pa6 i/o ft (4) spi1_miso / tim8_bkin/tim13_ch1 / dcmi_pixclk / tim3_ch1 / tim1_bkin / eventout adc12_in6 23 j8 32 43 r3 53 pa7 i/o ft (4) spi1_mosi/ tim8_ch1n / tim14_ch1/tim3_ch2/ eth_mii_rx_dv / tim1_ch1n / eth_rmii_crs_dv/ eventout adc12_in7 24 - 33 44 n5 54 pc4 i/o ft (4) eth_rmii_rx_d0 / eth_mii_rx_d0/ eventout adc12_in14 25 - 34 45 p5 55 pc5 i/o ft (4) eth_rmii_rx_d1 / eth_mii_rx_d1/ eventout adc12_in15 26 g7 35 46 r5 56 pb0 i/o ft (4) tim3_ch3 / tim8_ch2n/ otg_hs_ulpi_d1/ eth_mii_rxd2 / tim1_ch2n/ eventout adc12_in8 table 7. stm32f41x pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions a dditional functions lqfp64 wlcsp90 lqfp100 lqfp144 ufbga176 lqfp176
pinouts and pin description stm32f415xx, stm32f417xx 50/186 docid022063 rev 4 27 h7 36 47 r4 57 pb1 i/o ft (4) tim3_ch4 / tim8_ch3n/ otg_hs_ulpi_d2/ eth_mii_rxd3 / tim1_ch3n/ eventout adc12_in9 28 j7 37 48 m6 58 pb2/boot1 (pb2) i/o ft eventout - - - 49 r6 59 pf11 i/o ft dcmi_d12/ eventout - - - 50 p6 60 pf12 i/o ft fsmc_a6/ eventout ---51m861 v ss s ---52n862 v dd s - - - 53 n6 63 pf13 i/o ft fsmc_a7/ eventout - - - 54 r7 64 pf14 i/o ft fsmc_a8/ eventout - - - 55 p7 65 pf15 i/o ft fsmc_a9/ eventout - - - 56 n7 66 pg0 i/o ft fsmc_a10/ eventout - - - 57 m7 67 pg1 i/o ft fsmc_a11/ eventout - g63858 r8 68 pe7 i/oft fsmc_d4/tim1_etr/ eventout - h6 39 59 p8 69 pe8 i/o ft fsmc_d5/ tim1_ch1n/ eventout - j6 40 60 p9 70 pe9 i/o ft fsmc_d6/tim1_ch1/ eventout ---61m971 v ss s ---62n972 v dd s - f6 41 63 r9 73 pe10 i/o ft fsmc_d7/tim1_ch2n/ eventout - j5 42 64 p10 74 pe11 i/o ft fsmc_d8/tim1_ch2/ eventout - h54365r1075 pe12 i/oft fsmc_d9/tim1_ch3n/ eventout - g54466n11 76 pe13 i/oft fsmc_d10/tim1_ch3/ eventout table 7. stm32f41x pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions a dditional functions lqfp64 wlcsp90 lqfp100 lqfp144 ufbga176 lqfp176
docid022063 rev 4 51/186 stm32f415xx, stm32f417xx pinouts and pin description - f5 45 67 p11 77 pe14 i/o ft fsmc_d11/tim1_ch4/ eventout - g44668r11 78 pe15 i/oft fsmc_d12/tim1_bkin/ eventout 29 h4 47 69 r12 79 pb10 i/o ft spi2_sck / i2s2_ck / i2c2_scl/ usart3_tx / otg_hs_ulpi_d3 / eth_mii_rx_er / tim2_ch3/ eventout 30 j4 48 70 r13 80 pb11 i/o ft i2c2_sda/usart3_rx/ otg_hs_ulpi_d4 / eth_rmii_tx_en/ eth_mii_tx_en / tim2_ch4/ eventout 31 f4 49 71 m10 81 v cap_1 s 32 - 50 72 n10 82 v dd s ----m1183 ph6 i/oft i2c2_smba / tim12_ch1 / eth_mii_rxd2/ eventout - - - - n12 84 ph7 i/o ft i2c3_scl / eth_mii_rxd3/ eventout ----m1285 ph8 i/oft i2c3_sda / dcmi_hsync/ eventout ----m1386 ph9 i/oft i2c3_smba / tim12_ch2/ dcmi_d0/ eventout ----l1387 ph10 i/oft tim5_ch1 / dcmi_d1/ eventout ----l1288 ph11 i/oft tim5_ch2 / dcmi_d2/ eventout ----k1289 ph12 i/oft tim5_ch3 / dcmi_d3/ eventout ----h1290 v ss s ----j1291 v dd s table 7. stm32f41x pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions a dditional functions lqfp64 wlcsp90 lqfp100 lqfp144 ufbga176 lqfp176
pinouts and pin description stm32f415xx, stm32f417xx 52/186 docid022063 rev 4 33 j3 51 73 p12 92 pb12 i/o ft spi2_nss / i2s2_ws / i2c2_smba/ usart3_ck/ tim1_bkin / can2_rx / otg_hs_ulpi_d5/ eth_rmii_txd0 / eth_mii_txd0/ otg_hs_id/ eventout 34 j1 52 74 p13 93 pb13 i/o ft spi2_sck / i2s2_ck / usart3_cts/ tim1_ch1n /can2_tx / otg_hs_ulpi_d6 / eth_rmii_txd1 / eth_mii_txd1/ eventout otg_hs_vbus 35 j2 53 75 r14 94 pb14 i/o ft spi2_miso/ tim1_ch2n / tim12_ch1 / otg_hs_dm/ usart3_rts / tim8_ch2n/i2s2ext_sd/ eventout 36 h1 54 76 r15 95 pb15 i/o ft spi2_mosi / i2s2_sd/ tim1_ch3n / tim8_ch3n / tim12_ch2 / otg_hs_dp/ eventout rtc_refin - h2 55 77 p15 96 pd8 i/o ft fsmc_d13 / usart3_tx/ eventout - h3 56 78 p14 97 pd9 i/o ft fsmc_d14 / usart3_rx/ eventout - g3 57 79 n15 98 pd10 i/o ft fsmc_d15 / usart3_ck/ eventout - g15880n1499 pd11 i/oft fsmc_cle / fsmc_a16/usart3_ct s/ eventout - g25981n13100 pd12 i/oft fsmc_ale/ fsmc_a17/tim4_ch1 / usart3_rts/ eventout table 7. stm32f41x pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions a dditional functions lqfp64 wlcsp90 lqfp100 lqfp144 ufbga176 lqfp176
docid022063 rev 4 53/186 stm32f415xx, stm32f417xx pinouts and pin description - - 60 82 m15 101 pd13 i/o ft fsmc_a18/tim4_ch2/ eventout ---83-102 v ss s - - - 84 j13 103 v dd s - f2 61 85 m14 104 pd14 i/o ft fsmc_d0/tim4_ch3/ eventout/ eventout -f16286l14105 pd15 i/oft fsmc_d1/tim4_ch4/ eventout - - - 87 l15 106 pg2 i/o ft fsmc_a12/ eventout - - - 88 k15 107 pg3 i/o ft fsmc_a13/ eventout - - - 89 k14 108 pg4 i/o ft fsmc_a14/ eventout - - - 90 k13 109 pg5 i/o ft fsmc_a15/ eventout - - - 91 j15 110 pg6 i/o ft fsmc_int2/ eventout - - - 92 j14 111 pg7 i/o ft fsmc_int3 /usart6_ck/ eventout ---93h14112 pg8 i/oft usart6_rts / eth_pps_out/ eventout ---94g12113 v ss s ---95h13114 v dd s 37 f3 63 96 h15 115 pc6 i/o ft i2s2_mck / tim8_ch1/sdio_d6 / usart6_tx / dcmi_d0/tim3_ch1/ eventout 38 e1 64 97 g15 116 pc7 i/o ft i2s3_mck / tim8_ch2/sdio_d7 / usart6_rx / dcmi_d1/tim3_ch2/ eventout 39 e2 65 98 g14 117 pc8 i/o ft tim8_ch3/sdio_d0 /tim3_ch3/ usart6_ck / dcmi_d2/ eventout table 7. stm32f41x pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions a dditional functions lqfp64 wlcsp90 lqfp100 lqfp144 ufbga176 lqfp176
pinouts and pin description stm32f415xx, stm32f417xx 54/186 docid022063 rev 4 40 e3 66 99 f14 118 pc9 i/o ft i2s_ckin/ mco2 / tim8_ch4/sdio_d1 / /i2c3_sda / dcmi_d3 / tim3_ch4/ eventout 41 d1 67 100 f15 119 pa8 i/o ft mco1 / usart1_ck/ tim1_ch1/ i2c3_scl/ otg_fs_sof/ eventout 42 d2 68 101 e15 120 pa9 i/o ft usart1_tx/ tim1_ch2 / i2c3_smba / dcmi_d0/ eventout otg_fs_vbus 43 d3 69 102 d15 121 pa10 i/o ft usart1_rx/ tim1_ch3/ otg_fs_id/dcmi_d1/ eventout 44 c1 70 103 c15 122 pa11 i/o ft usart1_cts / can1_rx / tim1_ch4 / otg_fs_dm/ eventout 45 c2 71 104 b15 123 pa12 i/o ft usart1_rts / can1_tx/ tim1_etr/ otg_fs_dp/ eventout 46 d4 72 105 a15 124 pa13 (jtms-swdio) i/o ft jtms-swdio/ eventout 47 b1 73 106 f13 125 v cap_2 s - e7 74 107 f12 126 v ss s 48 e6 75 108 g13 127 v dd s - - - - e12 128 ph13 i/o ft tim8_ch1n / can1_tx/ eventout - - - - e13 129 ph14 i/o ft tim8_ch2n / dcmi_d4/ eventout ----d13130 ph15 i/oft tim8_ch3n / dcmi_d11/ eventout - c3 - - e14 131 pi0 i/o ft tim5_ch4 / spi2_nss / i2s2_ws / dcmi_d13/ eventout table 7. stm32f41x pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions a dditional functions lqfp64 wlcsp90 lqfp100 lqfp144 ufbga176 lqfp176
docid022063 rev 4 55/186 stm32f415xx, stm32f417xx pinouts and pin description - b2 - - d14 132 pi1 i/o ft spi2_sck / i2s2_ck / dcmi_d8/ eventout ----c14133 pi2 i/oft tim8_ch4 /spi2_miso / dcmi_d9 / i2s2ext_sd/ eventout ----c13134 pi3 i/oft tim8_etr / spi2_mosi / i2s2_sd / dcmi_d10/ eventout ----d9135 v ss s ----c9136 v dd s 49 a2 76 109 a14 137 pa14 (jtck/swclk) i/o ft jtck-swclk/ eventout 50 b3 77 110 a13 138 pa15 (jtdi) i/o ft jtdi/ spi3_nss/ i2s3_ws/tim2_ch1_et r / spi1_nss / eventout 51 d5 78 111 b14 139 pc10 i/o ft spi3_sck / i2s3_ck/ uart4_tx/sdio_d2 / dcmi_d8 / usart3_tx/ eventout 52 c4 79 112 b13 140 pc11 i/o ft uart4_rx/ spi3_miso / sdio_d3 / dcmi_d4/usart3_rx / i2s3ext_sd/ eventout 53 a3 80 113 a12 141 pc12 i/o ft uart5_tx/sdio_ck / dcmi_d9 / spi3_mosi /i2s3_sd / usart3_ck/ eventout - d6 81 114 b12 142 pd0 i/o ft fsmc_d2/can1_rx/ eventout - c5 82 115 c12 143 pd1 i/o ft fsmc_d3 / can1_tx/ eventout 54 b4 83 116 d12 144 pd2 i/o ft tim3_etr/uart5_rx/ sdio_cmd / dcmi_d11/ eventout table 7. stm32f41x pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions a dditional functions lqfp64 wlcsp90 lqfp100 lqfp144 ufbga176 lqfp176
pinouts and pin description stm32f415xx, stm32f417xx 56/186 docid022063 rev 4 - - 84 117 d11 145 pd3 i/o ft fsmc_clk/ usart2_cts/ eventout - a4 85 118 d10 146 pd4 i/o ft fsmc_noe/ usart2_rts/ eventout - c6 86 119 c11 147 pd5 i/o ft fsmc_nwe/usart2_tx / eventout - - - 120 d8 148 v ss s - - - 121 c8 149 v dd s - b5 87 122 b11 150 pd6 i/o ft fsmc_nwait/ usart2_rx/ eventout - a5 88 123 a11 151 pd7 i/o ft usart2_ck/fsmc_ne1/ fsmc_nce2/ eventout - - - 124 c10 152 pg9 i/o ft usart6_rx / fsmc_ne2/fsmc_nce3 / eventout - - - 125 b10 153 pg10 i/o ft fsmc_nce4_1/ fsmc_ne3/ eventout - - - 126 b9 154 pg11 i/o ft fsmc_nce4_2 / eth_mii_tx_en/ eth _rmii_tx_en/ eventout - - - 127 b8 155 pg12 i/o ft fsmc_ne4 / usart6_rts/ eventout - - - 128 a8 156 pg13 i/o ft fsmc_a24 / usart6_cts /eth_mii_txd0/ eth_rmii_txd0/ eventout - - - 129 a7 157 pg14 i/o ft fsmc_a25 / usart6_tx /eth_mii_txd1/ eth_rmii_txd1/ eventout table 7. stm32f41x pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions a dditional functions lqfp64 wlcsp90 lqfp100 lqfp144 ufbga176 lqfp176
docid022063 rev 4 57/186 stm32f415xx, stm32f417xx pinouts and pin description - e8 - 130 d7 158 v ss s - f7 - 131 c7 159 v dd s - - - 132 b7 160 pg15 i/o ft usart6_cts / dcmi_d13/ eventout 55 b6 89 133 a10 161 pb3 (jtdo/ traceswo) i/o ft jtdo/ traceswo/ spi3_sck / i2s3_ck / tim2_ch2 / spi1_sck/ eventout 56 a6 90 134 a9 162 pb4 (njtrst) i/o ft njtrst/ spi3_miso / tim3_ch1 / spi1_miso / i2s3ext_sd/ eventout 57 d7 91 135 a6 163 pb5 i/o ft i2c1_smba/ can2_rx / otg_hs_ulpi_d7 / eth_pps_out/tim3_ch 2 / spi1_mosi/ spi3_mosi / dcmi_d10 / i2s3_sd/ eventout 58 c7 92 136 b6 164 pb6 i/o ft i2c1_scl/ tim4_ch1 / can2_tx / dcmi_d5/usart1_tx/ eventout 59 b7 93 137 b5 165 pb7 i/o ft i2c1_sda / fsmc_nl / dcmi_vsync / usart1_rx/ tim4_ch2/ eventout 60 a7 94 138 d6 166 boot0 i b v pp 61 d8 95 139 a5 167 pb8 i/o ft tim4_ch3/sdio_d4/ tim10_ch1 / dcmi_d6 / eth_mii_txd3 / i2c1_scl/ can1_rx/ eventout 62 c8 96 140 b4 168 pb9 i/o ft spi2_nss/ i2s2_ws / tim4_ch4/ tim11_ch1/ sdio_d5 / dcmi_d7 / i2c1_sda / can1_tx/ eventout table 7. stm32f41x pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions a dditional functions lqfp64 wlcsp90 lqfp100 lqfp144 ufbga176 lqfp176
pinouts and pin description stm32f415xx, stm32f417xx 58/186 docid022063 rev 4 - - 97 141 a4 169 pe0 i/o ft tim4_etr / fsmc_nbl0 / dcmi_d2/ eventout - - 98 142 a3 170 pe1 i/o ft fsmc_nbl1 / dcmi_d3/ eventout 63 - 99 - d5 - v ss s - a8 - 143 c6 171 pdr_on i ft 64 a1 10 0 144 c5 172 v dd s - - - - d4 173 pi4 i/o ft tim8_bkin / dcmi_d5/ eventout - - - - c4 174 pi5 i/o ft tim8_ch1 / dcmi_vsync/ eventout - - - - c3 175 pi6 i/o ft tim8_ch2 / dcmi_d6/ eventout - - - - c2 176 pi7 i/o ft tim8_ch3 / dcmi_d7/ eventout 1. function availability depends on the chosen device. 2. pc13, pc14, pc15 and pi8 are supplied through the power switch . since the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 and pi8 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf. - these i/os must not be used as a current source (e.g. to drive an led). 3. main function after the first backup domain power-up. later on, it depends on the contents of the rtc registers even after reset (because these registers are not reset by the main reset) . for details on how to manage these i/os, refer to the rtc register description sections in the stm32f4xx reference manual, available fr om the stmicroelectronics website: www.st.com. 4. ft = 5 v tolerant except when in analog mode or oscillator mode (for pc14, pc15, ph0 and ph1). 5. if the device is delivered in an ufbga176 or wlcsp90 and t he bypass_reg pin is set to vdd (regulator off/internal reset on mode), then pa0 is used as an internal reset (active low). table 7. stm32f41x pin and ball definitions (continued) pin number pin name (function after reset) (1) pin type i / o structure notes alternate functions a dditional functions lqfp64 wlcsp90 lqfp100 lqfp144 ufbga176 lqfp176 table 8. fsmc pin definition pins (1) fsmc lqfp100 (2) wlcsp90 (2) cf nor/psram/ sram nor/psram mux nand 16 bit pe2 a23 a23 yes pe3 a19 a19 yes
docid022063 rev 4 59/186 stm32f415xx, stm32f417xx pinouts and pin description pe4 a20 a20 yes pe5 a21 a21 yes pe6 a22 a22 yes pf0 a0 a0 - - pf1 a1 a1 - - pf2 a2 a2 - - pf3 a3 a3 - - pf4 a4 a4 - - pf5 a5 a5 - - pf6 niord - - pf7 nreg - - pf8 niowr - - pf9 cd - - pf10 intr - - pf12 a6 a6 - - pf13 a7 a7 - - pf14 a8 a8 - - pf15 a9 a9 - - pg0 a10 a10 - - pg1 a11 - - pe7 d4 d4 da4 d4 yes yes pe8 d5 d5 da5 d5 yes yes pe9 d6 d6 da6 d6 yes yes pe10 d7 d7 da7 d7 yes yes pe11 d8 d8 da8 d8 yes yes pe12 d9 d9 da9 d9 yes yes pe13 d10 d10 da10 d10 yes yes pe14 d11 d11 da11 d11 yes yes pe15 d12 d12 da12 d12 yes yes pd8 d13 d13 da13 d13 yes yes pd9 d14 d14 da14 d14 yes yes pd10 d15 d15 da15 d15 yes yes pd11 a16 a16 cle yes yes table 8. fsmc pin definition (continued) pins (1) fsmc lqfp100 (2) wlcsp90 (2) cf nor/psram/ sram nor/psram mux nand 16 bit
pinouts and pin description stm32f415xx, stm32f417xx 60/186 docid022063 rev 4 pd12 a17 a17 ale yes yes pd13 a18 a18 yes pd14 d0 d0 da0 d0 yes yes pd15 d1 d1 da1 d1 yes yes pg2 a12 - - pg3 a13 - - pg4 a14 - - pg5 a15 - - pg6 int2 - - pg7 int3 - - pd0 d2 d2 da2 d2 yes yes pd1 d3 d3 da3 d3 yes yes pd3 clk clk yes pd4 noe noe noe noe yes yes pd5 nwe nwe nwe nwe yes yes pd6 nwait nwait nwait nwait yes yes pd7 ne1 ne1 nce2 yes yes pg9 ne2 ne2 nce3 - - pg10 nce4_1 ne3 ne3 - - pg11 nce4_2 - - pg12 ne4 ne4 - - pg13 a24 a24 - - pg14 a25 a25 - - pb7 nadv nadv yes yes pe0 nbl0 nbl0 yes pe1 nbl1 nbl1 yes 1. full fsmc features are available on lqfp144, lqfp176, and ufbga176. t he features available on smaller packages are given in the dedicated package column. 2. ports f and g are not available in devices delivered in 100-pin packages. table 8. fsmc pin definition (continued) pins (1) fsmc lqfp100 (2) wlcsp90 (2) cf nor/psram/ sram nor/psram mux nand 16 bit
stm32f415xx, stm32f417xx pinouts and pin description docid022063 rev 4 61/186 table 9. alternate function mapping port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/1 1 i2c1/2/3 spi1/spi2/ i2s 2/ i2s 2ext spi3/ i2s ext/ i2s 3 usart1/2/3/ i2s 3ext uart4/5/ usart6 can1/ can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_fs dcmi port a pa0 tim2_ch1_e tr tim 5_ch1 tim8_etr usart2_cts uart4_tx eth_mii_crs eventout pa1 tim2_ch2 tim5_ch2 usart2_rts uart4_rx eth_mii _rx_clk eth_rmii__ref _clk eventout pa2 tim2_ch3 tim5_ch3 tim9_ch1 usart2_tx eth_mdio eventout pa3 tim2_ch4 tim5_ch4 tim9_ch2 usart2_rx otg_hs_ulpi_ d0 eth _mii_col eventout pa4 spi1_nss spi3_nss i2s3_ws usart2_ck otg_hs_so f dcmi_hsyn c eventout pa5 tim2_ch1_e tr tim8_ch1n spi1_sck otg_hs_ulpi_ ck eventout pa6 tim1_bkin tim3_ch1 tim8_bkin spi1_miso tim13_ch1 dcmi_pixck eventout pa7 tim1_ch1n tim3_ch2 tim8_ch1n spi1_mosi tim14_ch1 eth_mii _rx_dv eth_rmii _crs_dv eventout pa8 mco1 tim1_ch1 i2c3_scl us art1_ck otg_fs_sof eventout pa9 tim1_ch2 i2c3_smb a usart1_tx dcmi_d0 eventout pa10 tim1_ch3 usart1_rx otg_fs_id dcmi_d1 eventout pa11 tim1_ch4 usart1_cts can1_rx otg_fs_dm eventout pa12 tim1_etr usart1_rts can1_tx otg_fs_dp eventout pa13 jtms- swdio eventout pa14 jtck- swclk eventout pa15 jtdi tim 2_ch1 tim 2_etr spi1_nss spi3_nss/ i2s3_ws eventout
pinouts and pin description stm32f415xx, stm32f417xx 62/186 docid022063 rev 4 port b pb0 tim1_ch2n tim3_ch3 tim8_ch2n otg_hs_ulpi_ d1 eth _mii_rxd2 eventout pb1 tim1_ch3n tim3_ch4 tim8_ch3n otg_hs_ulpi_ d2 eth _mii_rxd3 eventout pb2 eventout pb3 jtdo/ traces wo tim2_ch2 spi1_sck spi3_sck i2s3_ck eventout pb4 njtrst tim3_ch1 spi1_miso spi3_miso i2s3ext_sd eventout pb5 tim3_ch2 i2c1_smb a spi1_mosi spi3_mosi i2s3_sd can2_rx otg_hs_ulpi_ d7 eth _pps_out dcmi_d10 eventout pb6 tim4_ch1 i2c1_scl usart1_tx can2_tx dcmi_d5 eventout pb7 tim4_ch2 i2c1_sda usart1_rx fsmc_nl dcmi_vsyn c eventout pb8 tim4_ch3 tim10_ch1 i2c1_scl can1_rx eth _mii_txd3 sdio_d4 dcmi_d6 eventout pb9 tim4_ch4 tim11_ch1 i2c1_sda spi2_nss i2s2_ws can1_tx sdio_d5 dcmi_d7 eventout pb10 tim2_ch3 i2c2_scl spi2_sck i2s2_ck usart3_tx otg_hs_ulpi_ d3 eth_ mii_rx_er eventout pb11 tim2_ch4 i2c2_sda usart3_rx otg_hs_ulpi_ d4 eth _mii_tx_en eth _rmii_tx_en eventout pb12 tim1_bkin i2c2_smb a spi2_nss i2s2_ws usart3_ck can2_rx otg_hs_ulpi_ d5 eth _mii_txd0 eth _rmii_txd0 otg_hs_id eventout pb13 tim1_ch1n spi2_sck i2s2_ck usart3_cts can2_tx otg_hs_ulpi_ d6 eth _mii_txd1 eth _rmii_txd1 eventout pb14 tim1_ch2n tim8_ch2n spi2_miso i2s2ext_sd usart3_rts tim12_ch1 otg_hs_dm eventout pb15 rtc_ refin tim1_ch3n tim8_ch3n spi2_mosi i2s2_sd tim12_ch2 otg_hs_dp eventout table 9. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/1 1 i2c1/2/3 spi1/spi2/ i2s 2/ i2s 2ext spi3/ i2s ext/ i2s 3 usart1/2/3/ i2s 3ext uart4/5/ usart6 can1/ can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_fs dcmi
stm32f415xx, stm32f417xx pinouts and pin description docid022063 rev 4 63/186 port c pc0 otg_hs_ulpi_ stp eventout pc1 eth_mdc eventout pc2 spi2_miso i2s2ext_sd otg_hs_ulpi_ dir eth _mii_txd2 eventout pc3 spi2_mosi i2s2_sd otg_hs_ulpi_ nxt eth _mii_tx_clk eventout pc4 eth_mii_rxd0 eth_rmii_rxd0 eventout pc5 eth _mii_rxd1 eth _rmii_rxd1 eventout pc6 tim3_ch1 tim8_ch1 i2s2_mck usart6_tx sdio_d6 dcmi_d0 eventout pc7 tim3_ch2 tim8_ch2 i2s3_mck usart6_rx sdio_d7 dcmi_d1 eventout pc8 tim3_ch3 tim8_ch3 usart6_ck sdio_d0 dcmi_d2 eventout pc9 mco2 tim3_ch4 tim8_ch4 i2c3_sda i2s_ckin sdio_d1 dcmi_d3 eventout pc10 spi3_sck/ i2s3_ck usart3_tx/ uart4_tx sdio_d2 dcmi_d8 eventout pc11 i2s3ext_sd spi3_miso/ usart3_rx uart4_rx sdio_d3 dcmi_d4 eventout pc12 spi3_mosi i2s3_sd usart3_ck uart5_tx sdio_ck dcmi_d9 eventout pc13 eventout pc14 eventout pc15 eventout table 9. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/1 1 i2c1/2/3 spi1/spi2/ i2s 2/ i2s 2ext spi3/ i2s ext/ i2s 3 usart1/2/3/ i2s 3ext uart4/5/ usart6 can1/ can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_fs dcmi
pinouts and pin description stm32f415xx, stm32f417xx 64/186 docid022063 rev 4 port d pd0 can1_rx fsmc_d2 eventout pd1 can1_tx fsmc_d3 eventout pd2 tim3_etr uart5_rx sdio_cmd dcmi_d11 eventout pd3 usart2_cts fsmc_clk eventout pd4 usart2_rts fsmc_noe eventout pd5 usart2_tx fsmc_nwe eventout pd6 usart2_rx fsmc_nwait eventout pd7 usart2_ck fsmc_ne1/ fsmc_nce2 eventout pd8 usart3_tx fsmc_d13 eventout pd9 usart3_rx fsmc_d14 eventout pd10 usart3_ck fsmc_d15 eventout pd11 usart3_cts fsmc_a16 eventout pd12 tim4_ch1 usart3_rts fsmc_a17 eventout pd13 tim4_ch2 fsmc_a18 eventout pd14 tim4_ch3 fsmc_d0 eventout pd15 tim4_ch4 fsmc_d1 eventout table 9. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/1 1 i2c1/2/3 spi1/spi2/ i2s 2/ i2s 2ext spi3/ i2s ext/ i2s 3 usart1/2/3/ i2s 3ext uart4/5/ usart6 can1/ can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_fs dcmi
stm32f415xx, stm32f417xx pinouts and pin description docid022063 rev 4 65/186 port e pe0 tim4_etr fsmc_nbl0 dcmi_d2 eventout pe1 fsmc_nbl1 dcmi_d3 eventout pe2 tracecl k eth _mii_txd3 fsmc_a23 eventout pe3 traced0 fsmc_a19 eventout pe4 traced1 fsmc_a20 dcmi_d4 eventout pe5 traced2 tim9_ch1 fsmc_a21 dcmi_d6 eventout pe6 traced3 tim9_ch2 fsmc_a22 dcmi_d7 eventout pe7 tim1_etr fsmc_d4 eventout pe8 tim1_ch1n fsmc_d5 eventout pe9 tim1_ch1 fsmc_d6 eventout pe10 tim1_ch2n fsmc_d7 eventout pe11 tim1_ch2 fsmc_d8 eventout pe12 tim1_ch3n fsmc_d9 eventout pe13 tim1_ch3 fsmc_d10 eventout pe14 tim1_ch4 fsmc_d11 eventout pe15 tim1_bkin fsmc_d12 eventout table 9. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/1 1 i2c1/2/3 spi1/spi2/ i2s 2/ i2s 2ext spi3/ i2s ext/ i2s 3 usart1/2/3/ i2s 3ext uart4/5/ usart6 can1/ can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_fs dcmi
pinouts and pin description stm32f415xx, stm32f417xx 66/186 docid022063 rev 4 port f pf0 i2c2_sda fsmc_a0 eventout pf1 i2c2_scl fsmc_a1 eventout pf2 i2c2_ smba fsmc_a2 eventout pf3 fsmc_a3 eventout pf4 fsmc_a4 eventout pf5 fsmc_a5 eventout pf6 tim10_ch1 fsmc_niord eventout pf7 tim11_ch1 fsmc_nreg eventout pf8 tim13_ch1 fsmc_ niowr eventout pf9 tim14_ch1 fsmc_cd eventout pf10 fsmc_intr eventout pf11 dcmi_d12 eventout pf12 fsmc_a6 eventout pf13 fsmc_a7 eventout pf14 fsmc_a8 eventout pf15 fsmc_a9 eventout table 9. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/1 1 i2c1/2/3 spi1/spi2/ i2s 2/ i2s 2ext spi3/ i2s ext/ i2s 3 usart1/2/3/ i2s 3ext uart4/5/ usart6 can1/ can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_fs dcmi
stm32f415xx, stm32f417xx pinouts and pin description docid022063 rev 4 67/186 port g pg0 fsmc_a10 eventout pg1 fsmc_a11 eventout pg2 fsmc_a12 eventout pg3 fsmc_a13 eventout pg4 fsmc_a14 eventout pg5 fsmc_a15 eventout pg6 fsmc_int2 eventout pg7 usart6_ck fsmc_int3 eventout pg8 usart6_ rts eth _pps_out eventout pg9 usart6_rx fsmc_ne2/ fsmc_nce3 eventout pg10 fsmc_ nce4_1/ fsmc_ne3 eventout pg11 eth _mii_tx_en eth _rmii_ tx_en fsmc_nce4_ 2 eventout pg12 usart6_ rts fsmc_ne4 eventout pg13 uart6_cts eth _mii_txd0 eth _rmii_txd0 fsmc_a24 eventout pg14 usart6_tx eth _mii_txd1 eth _rmii_txd1 fsmc_a25 eventout pg15 usart6_ cts dcmi_d13 eventout table 9. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/1 1 i2c1/2/3 spi1/spi2/ i2s 2/ i2s 2ext spi3/ i2s ext/ i2s 3 usart1/2/3/ i2s 3ext uart4/5/ usart6 can1/ can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_fs dcmi
pinouts and pin description stm32f415xx, stm32f417xx 68/186 docid022063 rev 4 port h ph0 eventout ph1 eventout ph2 eth _mii_crs eventout ph3 eth _mii_col eventout ph4 i2c2_scl otg_hs_ulpi_ nxt eventout ph5 i2c2_sda eventout ph6 i2c2_smb a tim12_ch1 eth _mii_rxd2 eventout ph7 i2c3_scl eth _mii_rxd3 eventout ph8 i2c3_sda dcmi_hsyn c eventout ph9 i2c3_smb a tim12_ch2 dcmi_d0 eventout ph10 tim5_ch1 dcmi_d1 eventout ph11 tim5_ch2 dcmi_d2 eventout ph12 tim5_ch3 dcmi_d3 eventout ph13 tim8_ch1n can1_tx eventout ph14 tim8_ch2n dcmi_d4 eventout ph15 tim8_ch3n dcmi_d11 eventout table 9. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/1 1 i2c1/2/3 spi1/spi2/ i2s 2/ i2s 2ext spi3/ i2s ext/ i2s 3 usart1/2/3/ i2s 3ext uart4/5/ usart6 can1/ can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_fs dcmi
stm32f415xx, stm32f417xx pinouts and pin description docid022063 rev 4 69/186 port i pi0 tim5_ch4 spi2_nss i2s2_ws dcmi_d13 eventout pi1 spi2_sck i2s2_ck dcmi_d8 eventout pi2 tim8_ch4 spi2_miso i2s2ext_sd dcmi_d9 eventout pi3 tim8_etr spi2_mosi i2s2_sd dcmi_d10 eventout pi4 tim8_bkin dcmi_d5 eventout pi5 tim8_ch1 dcmi_ vsync eventout pi6 tim8_ch2 dcmi_d6 eventout pi7 tim8_ch3 dcmi_d7 eventout pi8 eventout pi9 can1_rx eventout pi10 eth _mii_rx_er eventout pi11 otg_hs_ulpi_ dir eventout table 9. alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/1 1 i2c1/2/3 spi1/spi2/ i2s 2/ i2s 2ext spi3/ i2s ext/ i2s 3 usart1/2/3/ i2s 3ext uart4/5/ usart6 can1/ can2/ tim12/13/14 otg_fs/ otg_hs eth fsmc/sdio/ otg_fs dcmi
memory mapping stm32f415xx, stm32f417xx 70/186 docid022063 rev 4 4 memory mapping the memory map is shown in figure 18 . figure 18. stm32f41x memory map 512-mbyte block 7 cortex-m4's internal peripherals 512-mbyte block 6 not used 512-mbyte block 5 fsmc registers 512-mbyte block 4 fsmc bank 3 & bank4 512-mbyte block 3 fsmc bank1 & bank2 512-mbyte block 2 peripherals 512-mbyte block 1 sram 0x0000 0000 0x1fff ffff 0x2000 0000 0x3fff ffff 0x4000 0000 0x5fff ffff 0x6000 0000 0x7fff ffff 0x8000 0000 0x9fff ffff 0xa000 0000 0xbfff ffff 0xc000 0000 0xdfff ffff 0xe000 0000 0xffff ffff 512-mbyte block 0 code flash 0x0810 0000 - 0x0fff ffff 0x1fff 0000 - 0x1fff 7a0f 0x1fff c000 - 0x1fff c007 0x0800 0000 - 0x080f ffff 0x0010 0000 - 0x07ff ffff 0x0000 0000 - 0x000f ffff system memory + otp reserved reserved aliased to flash, system memory or sram depending on the boot pins sram (16 kb aliased by bit-banding) reserved 0x2000 0000 - 0x2001 bfff 0x2001 c000 - 0x2001 ffff 0x2002 0000 - 0x3fff ffff 0x4000 0000 reserved 0x4000 7fff 0x4000 7800 - 0x4000 ffff 0x4001 0000 0x4001 57ff 0x4002 000 reserved 0x5006 0c00 - 0x5fff ffff 0x6000 0000 ahb3 0xa000 0fff 0xa000 1000 - 0xdfff ffff ai18513f option bytes reserved 0x4001 5800 - 0x4001 ffff 0x5006 0bff ahb2 0x5000 0000 0x4008 0000 - 0x4fff ffff reserved ahb1 sram (112 kb aliased by bit-banding) reserved 0x1fff c008 - 0x1fff ffff 0x1fff 7a10 - 0x1fff 7fff reserved ccm data ram (64 kb data sram) 0x1000 0000 - 0x1000 ffff reserved 0x1001 0000 - 0x1ffe ffff reserved apb2 0x4007 ffff apb1 cortex-m4 internal peripherals 0xe000 0000 - 0xe00f ffff reserved 0xe010 0000 - 0xffff ffff
docid022063 rev 4 71/186 stm32f415xx, stm32f417xx memory mapping table 10. stm32f41x register boundary addresses bus boundary address peripheral 0xe00f ffff - 0xffff ffff reserved cortex-m4 0xe000 0000 - 0xe00f ffff cortex-m4 internal peripherals 0xa000 1000 - 0xdfff ffff reserved ahb3 0xa000 0000 - 0xa000 0fff fsmc control register 0x9000 0000 - 0x9fff ffff fsmc bank 4 0x8000 0000 - 0x8fff ffff fsmc bank 3 0x7000 0000 - 0x7fff ffff fsmc bank 2 0x6000 0000 - 0x6fff ffff fsmc bank 1 0x5006 0c00- 0x5fff ffff reserved ahb2 0x5006 0800 - 0x5006 0bff rng 0x5006 0400 - 0x5006 07ff hash 0x5006 0000 - 0x5006 03ff cryp 0x5005 0400 - 0x5005 ffff reserved 0x5005 0000 - 0x5005 03ff dcmi 0x5004 0000- 0x5004 ffff reserved 0x5000 0000 - 0x5003 ffff usb otg fs 0x4008 0000- 0x4fff ffff reserved
memory mapping stm32f415xx, stm32f417xx 72/186 docid022063 rev 4 ahb1 0x4004 0000 - 0x4007 ffff usb otg hs 0x4002 9400 - 0x4003 ffff reserved 0x4002 9000 - 0x4002 93ff ethernet mac 0x4002 8c00 - 0x4002 8fff 0x4002 8800 - 0x4002 8bff 0x4002 8400 - 0x4002 87ff 0x4002 8000 - 0x4002 83ff 0x4002 6800 - 0x4002 7fff reserved 0x4002 6400 - 0x4002 67ff dma2 0x4002 6000 - 0x4002 63ff dma1 0x4002 5000 - 0x4002 5fff reserved 0x4002 4000 - 0x4002 4fff bkpsram 0x4002 3c00 - 0x4002 3fff flash interface register 0x4002 3800 - 0x4002 3bff rcc 0x4002 3400 - 0x4002 37ff reserved 0x4002 3000 - 0x4002 33ff crc 0x4002 2400 - 0x4002 2fff reserved 0x4002 2000 - 0x4002 23ff gpioi 0x4002 1c00 - 0x4002 1fff gpioh 0x4002 1800 - 0x4002 1bff gpiog 0x4002 1400 - 0x4002 17ff gpiof 0x4002 1000 - 0x4002 13ff gpioe 0x4002 0c00 - 0x4002 0fff gpiod 0x4002 0800 - 0x4002 0bff gpioc 0x4002 0400 - 0x4002 07ff gpiob 0x4002 0000 - 0x4002 03ff gpioa 0x4001 5800- 0x4001 ffff reserved table 10. stm32f41x register boundary addresses (continued) bus boundary address peripheral
docid022063 rev 4 73/186 stm32f415xx, stm32f417xx memory mapping apb2 0x4001 4c00 - 0x4001 57ff reserved 0x4001 4800 - 0x4001 4bff tim11 0x4001 4400 - 0x4001 47ff tim10 0x4001 4000 - 0x4001 43ff tim9 0x4001 3c00 - 0x4001 3fff exti 0x4001 3800 - 0x4001 3bff syscfg 0x4001 3400 - 0x4001 37ff reserved 0x4001 3000 - 0x4001 33ff spi1 0x4001 2c00 - 0x4001 2fff sdio 0x4001 2400 - 0x4001 2bff reserved 0x4001 2000 - 0x4001 23ff adc1 - adc2 - adc3 0x4001 1800 - 0x4001 1fff reserved 0x4001 1400 - 0x4001 17ff usart6 0x4001 1000 - 0x4001 13ff usart1 0x4001 0800 - 0x4001 0fff reserved 0x4001 0400 - 0x4001 07ff tim8 0x4001 0000 - 0x4001 03ff tim1 0x4000 7800- 0x4000 ffff reserved table 10. stm32f41x register boundary addresses (continued) bus boundary address peripheral
memory mapping stm32f415xx, stm32f417xx 74/186 docid022063 rev 4 apb1 0x4000 7800 - 0x4000 7fff reserved 0x4000 7400 - 0x4000 77ff dac 0x4000 7000 - 0x4000 73ff pwr 0x4000 6c00 - 0x4000 6fff reserved 0x4000 6800 - 0x4000 6bff can2 0x4000 6400 - 0x4000 67ff can1 0x4000 6000 - 0x4000 63ff reserved 0x4000 5c00 - 0x4000 5fff i2c3 0x4000 5800 - 0x4000 5bff i2c2 0x4000 5400 - 0x4000 57ff i2c1 0x4000 5000 - 0x4000 53ff uart5 0x4000 4c00 - 0x4000 4fff uart4 0x4000 4800 - 0x4000 4bff usart3 0x4000 4400 - 0x4000 47ff usart2 0x4000 4000 - 0x4000 43ff i2s3ext 0x4000 3c00 - 0x4000 3fff spi3 / i2s3 0x4000 3800 - 0x4000 3bff spi2 / i2s2 0x4000 3400 - 0x4000 37ff i2s2ext 0x4000 3000 - 0x4000 33ff iwdg 0x4000 2c00 - 0x4000 2fff wwdg 0x4000 2800 - 0x4000 2bff rtc & bkp registers 0x4000 2400 - 0x4000 27ff reserved 0x4000 2000 - 0x4000 23ff tim14 0x4000 1c00 - 0x4000 1fff tim13 0x4000 1800 - 0x4000 1bff tim12 0x4000 1400 - 0x4000 17ff tim7 0x4000 1000 - 0x4000 13ff tim6 0x4000 0c00 - 0x4000 0fff tim5 0x4000 0800 - 0x4000 0bff tim4 0x4000 0400 - 0x4000 07ff tim3 0x4000 0000 - 0x4000 03ff tim2 table 10. stm32f41x register boundary addresses (continued) bus boundary address peripheral
docid022063 rev 4 75/186 stm32f415xx, stm32f417xx electrical characteristics 5 electrical characteristics 5.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 5.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 5.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.3 v (for the 1.8 v v dd 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 5.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 19 . 5.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 20 . figure 19. pin loading conditi ons figure 20. pin input voltage ms19011v1 c = 50 pf stm32f pin osc_out (hi-z when using hse or lse) ms19010v1 stm32f pin v in osc_out (hi-z when using hse or lse)
electrical characteristics stm32f415xx, stm32f417xx 76/186 docid022063 rev 4 5.1.6 power supply scheme figure 21. power supply scheme 1. each power supply pair must be decoupled with filt ering ceramic capacitors as shown above. these capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the pcb to ensure the good functionality of the device. 2. to connect bypass_reg and pdr_on pins, refer to section 2.2.16: voltage regulator and table 2.2.15: power supply supervisor . 3. the two 2.2 f ceramic capacitors should be repl aced by two 100 nf decoupling capacitors when the voltage regulator is off. 4. the 4.7 f ceramic capacitor must be connected to one of the v dd pin. 5. v dda =v dd and v ssa =v ss . ms19911v2 backup circuitry (osc32k,rtc, wakeup logic backup registers, backup ram) kernel logic (cpu, digital & ram) analog: rcs, pll,.. power switch vbat gpios out in 15 100 nf + 1 4.7 f vbat = 1.65 to 3.6v voltage regulator vdda adc level shifter io logic vdd 100 nf + 1 f flash memory vcap_1 vcap_2 2 2.2 f bypass_reg pdr_on reset controller vdd 1/2/...14/15 vss 1/2/...14/15 vdd vref+ vref- vssa vref 100 nf + 1 f
docid022063 rev 4 77/186 stm32f415xx, stm32f417xx electrical characteristics 5.1.7 current consumption measurement figure 22. current consum ption measurement scheme 5.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 11: voltage characteristics , table 12: current characteristics , and table 13: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability. ai14126 v bat v dd v dda i dd _v bat i dd table 11. voltage characteristics symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda , v dd ) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. ?0.3 4.0 v v in input voltage on five-volt tolerant pin (2) 2. v in maximum value must always be respected. refer to table 12 for the values of the maximum allowed injected current. v ss ?0.3 v dd +4 input voltage on any other pin v ss ?0.3 4.0 | v ddx | variations between different v dd power pins - 50 mv |v ssx ? v ss | variations between all the different ground pins - 50 v esd(hbm) electrostatic discharge voltage (human body model) see section 5.3.14: absolute maximum ratings (electrical sensitivity)
electrical characteristics stm32f415xx, stm32f417xx 78/186 docid022063 rev 4 5.3 operating conditions 5.3.1 general operating conditions table 12. current characteristics symbol ratings max. unit i vdd total current into v dd power lines (source) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 150 ma i vss total current out of v ss ground lines (sink) (1) 150 i io output current sunk by any i/o and control pin 25 output current source by any i/os and control pin 25 i inj(pin) (2) 2. negative injection disturbs the analog performance of the device. see note in section 5.3.20: 12-bit adc characteristics . injected current on five-volt tolerant i/o (3) 3. positive injection is not possible on thes e i/os. a negative injection is induced by v in v dd while a negative injection is induced by v in docid022063 rev 4 79/186 stm32f415xx, stm32f417xx electrical characteristics v 12 regulator on: 1.2 v internal voltage on v cap_1 /v cap_2 pins vos bit in pwr_cr register = 0 (1) max frequency 144mhz 1.08 1.14 1.20 v vos bit in pwr_cr register= 1 max frequency 168mhz 1.20 1.26 1.32 v regulator off: 1.2 v external voltage must be supplied from external regulator on v cap_1 /v cap_2 pins max frequency 144mhz 1.10 1.14 1.20 v max frequency 168mhz 1.20 1.26 1.30 v v in input voltage on rst and ft pins (6) 2v v dd 3.6 v ?0.3 - 5.5 v v dd 2 v ?0.3 - 5.2 input voltage on tta pins ?0.3 - v dda + 0.3 input voltage on b pin - 5.5 p d power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (7) lqfp64 - 435 mw lqfp100 - 465 lqfp144 - 500 lqfp176 - 526 ufbga176 - 513 wlcsp90 - 543 t a ambient temperature for 6 suffix version maximum power dissipation ?40 85 c low power dissipation (8) ?40 105 ambient temperature for 7 suffix version maximum power dissipation ?40 105 c low power dissipation (8) ?40 125 t j junction temperature range 6 suffix version ?40 105 c 7 suffix version ?40 125 1. the average expected gain in power consumption when vo s = 0 compared to vos = 1 is around 10% for the whole temperature range, when the system cl ock frequency is between 30 and 144 mhz. 2. v dd /v dda minimum value of 1.7 v is obtained when the device operat es in reduced temperature range, and with the use of an external power supply supervisor (refer to section : internal reset off ). 3. when the adc is used, refer to table 67: adc characteristics . 4. if v ref+ pin is present, it must res pect the following condition: v dda -v ref+ < 1.2 v. 5. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and power-down operation. 6. to sustain a voltage higher than v dd +0.3, the internal pull-up and pull-down resistors must be disabled. 7. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax . 8. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax . table 14. general operating conditions (continued) symbol parameter conditions min typ max unit
electrical characteristics stm32f415xx, stm32f417xx 80/186 docid022063 rev 4 5.3.2 v cap_1 /v cap_2 external capacitor stabilization for the main regula tor is achieved by connecting an external capacitor c ext to the v cap_1 /v cap_2 pins. c ext is specified in table 16 . table 15. limitations depending on the operating power supply range operating power supply range adc operation maximum flash memory access frequency with no wait state (f flashmax ) maximum flash memory access frequency with wait states (1) (2) i/o operation clock output frequency on i/o pins possible flash memory operations v dd =1.8 to 2.1 v (3) conversion time up to 1.2 msps 20 mhz (4) 160 mhz with 7 wait states ? degraded speed performance ? no i/o compensation up to 30 mhz 8-bit erase and program operations only v dd = 2.1 to 2.4 v conversion time up to 1.2 msps 22 mhz 168 mhz with 7 wait states ? degraded speed performance ? no i/o compensation up to 30 mhz 16-bit erase and program operations v dd = 2.4 to 2.7 v conversion time up to 2.4 msps 24 mhz 168 mhz with 6 wait states ? degraded speed performance ?i/o compensation works up to 48 mhz 16-bit erase and program operations v dd = 2.7 to 3.6 v (5) conversion time up to 2.4 msps 30 mhz 168 mhz with 5 wait states ? full-speed operation ?i/o compensation works ?up to 60 mhz when v dd = 3.0 to 3.6 v ?up to 48 mhz when v dd = 2.7 to 3.0 v 32-bit erase and program operations 1. it applies only when code executed from flash memory access, when code executed from ram, no wait state is required. 2. thanks to the art accelerator and the 128-bit flash memory, the number of wait states given here does not impact the execution speed from flash memory since the art accelerator allows to achieve a performance equivalent to 0 wait state program execution. 3. v dd /vdda minimum value of 1.7 v is obt ained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to section : internal reset off ). 4. prefetch is not available. refe r to an3430 application note for details on how to adjust performance and power. 5. the voltage range for otg usb fs can drop down to 2.7 v. however it is degraded between 2.7 and 3 v.
docid022063 rev 4 81/186 stm32f415xx, stm32f417xx electrical characteristics figure 23. external capacitor c ext 1. legend: esr is the equivalent series resistance. 5.3.3 operating conditi ons at power-up / powe r-down (regulator on) subject to general operating conditions for t a . 5.3.4 operating conditi ons at power-up / powe r-down (regulator off) subject to general operating conditions for t a . 5.3.5 embedded reset and power control block characteristics the parameters given in table 19 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 14 . table 16. v cap_1 /v cap_2 operating conditions (1) 1. when bypassing the voltage regulator, the two 2.2 f v cap capacitors are not required and should be replaced by two 100 nf decoupling capacitors. symbol parameter conditions cext capacitance of external capacitor 2.2 f esr esr of external capacitor < 2 ms19044v2 esr r leak c table 17. operating conditions at power-up / power-down (regulator on) symbol parameter min max unit t vdd v dd rise time rate 20 s/v v dd fall time rate 20 table 18. operating conditions at pow er-up / power-down (regulator off) (1) 1. to reset the internal logic at power-down, a reset must be applied on pin pa0 when v dd reach below minimum value of v 12 . symbol parameter co nditions min max unit t vdd v dd rise time rate power-up 20 s/v v dd fall time rate power-down 20 t vcap v cap_1 and v cap_2 rise time rate power-up 20 v cap_1 and v cap_2 fall time rate power-down 20
electrical characteristics stm32f415xx, stm32f417xx 82/186 docid022063 rev 4 table 19. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v pvd programmable voltage detector level selection pls[2:0]=000 (rising edge) 2.09 2.14 2.19 v pls[2:0]=000 (falling edge) 1.98 2.04 2.08 v pls[2:0]=001 (rising edge) 2.23 2.30 2.37 v pls[2:0]=001 (falling edge) 2.13 2.19 2.25 v pls[2:0]=010 (rising edge) 2.39 2.45 2.51 v pls[2:0]=010 (falling edge) 2.29 2.35 2.39 v pls[2:0]=011 (rising edge) 2.54 2.60 2.65 v pls[2:0]=011 (falling edge) 2.44 2.51 2.56 v pls[2:0]=100 (rising edge) 2.70 2.76 2.82 v pls[2:0]=100 (falling edge) 2.59 2.66 2.71 v pls[2:0]=101 (rising edge) 2.86 2.93 2.99 v pls[2:0]=101 (falling edge) 2.65 2.84 3.02 v pls[2:0]=110 (rising edge) 2.96 3.03 3.10 v pls[2:0]=110 (falling edge) 2.85 2.93 2.99 v pls[2:0]=111 (rising edge) 3.07 3.14 3.21 v pls[2:0]=111 (falling edge) 2.95 3.03 3.09 v v pvdhyst (1) pvd hysteresis - 100 - mv v por/pdr power-on/power-down reset threshold falling edge 1.60 1.68 1.76 v rising edge 1.64 1.72 1.80 v v pdrhyst (1) pdr hysteresis - 40 - mv v bor1 brownout level 1 threshold falling edge 2.13 2.19 2.24 v rising edge 2.23 2.29 2.33 v v bor2 brownout level 2 threshold falling edge 2.44 2.50 2.56 v rising edge 2.53 2.59 2.63 v v bor3 brownout level 3 threshold falling edge 2.75 2.83 2.88 v rising edge 2.85 2.92 2.97 v
docid022063 rev 4 83/186 stm32f415xx, stm32f417xx electrical characteristics 5.3.6 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pi n loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 22: current consumption measurement scheme . all run mode current consumption measurements given in this section are performed using a coremark-compliant code. typical and maximum current consumption the mcu is placed under the following conditions: ? at startup, all i/o pins are configured as analog inputs by firmware. ? all peripherals are disabled except if it is explicitly mentioned. ? the flash memory access time is adjusted to f hclk frequency (0 wait state from 0 to 30 mhz, 1 wait state from 30 to 60 mhz, 2 wait states from 60 to 90 mhz, 3 wait states from 90 to 120 mhz, 4 wait states from 120 to 150 mhz, and 5 wait states from 150 to 168 mhz). ? when the peripherals are enabled hclk is the system clock, f pclk1 = f hclk /4, and f pclk2 = f hclk /2, except is explicitly mentioned. ? the maximum values are obtained for v dd = 3.6 v and maximum ambient temperature (t a ), and the typical values for t a = 25 c and v dd = 3.3 v unless otherwise specified. v borhyst (1) bor hysteresis - 100 - mv t rsttempo (1)(2) reset temporization 0.5 1.5 3.0 ms i rush (1) inrush current on voltage regulator power-on (por or wakeup from standby) - 160 200 ma e rush (1) inrush energy on voltage regulator power-on (por or wakeup from standby) v dd = 1.8 v, t a = 105 c, i rush = 171 ma for 31 s --5.4c 1. guaranteed by design, not tested in production. 2. the reset temporization is measured from the power-on (por reset or wakeup from v bat ) to the instant when first instruction is read by the user application code. table 19. embedded reset and power control block characteristics (continued) symbol parameter conditions min typ max unit
electrical characteristics stm32f415xx, stm32f417xx 84/186 docid022063 rev 4 table 20. typical and maximum current consumpt ion in run mode, code with data processing running from flash memory (art accelerator enabled) or ram (1) symbol parameter conditions f hclk typ max (2) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode external clock (3) , all peripherals enabled (4)(5) 168 mhz 87 102 109 ma 144 mhz 67 80 86 120 mhz 56 69 75 90 mhz 44 56 62 60 mhz 30 42 49 30 mhz 16 28 35 25 mhz 12 24 31 16 mhz (6) 92028 8 mhz 5 17 24 4 mhz 3 15 22 2 mhz 2 14 21 external clock (3) , all peripherals disabled (4)(5) 168 mhz 40 54 61 144 mhz 31 43 50 120 mhz 26 38 45 90 mhz 20 32 39 60 mhz 14 26 33 30 mhz 8 20 27 25 mhz 6 18 25 16 mhz (6) 51624 8 mhz 3 15 22 4 mhz 2 14 21 2 mhz 2 14 21 1. code and data processing running from sram1 using boot pins. 2. based on characterization, tested in production at v dd max and f hclk max with peripherals enabled. 3. external clock is 4 mhz and pll is on when f hclk > 25 mhz. 4. when the adc is on (adon bit set in the adc_cr2 register ), add an additional power consumption of 1.6 ma per adc for the analog part. 5. when analog peripheral blocks such as adcs, dacs, hse, lse, hsi, or lsi ar e on, an additional power consumption should be considered. 6. in this case hclk = system clock/2.
docid022063 rev 4 85/186 stm32f415xx, stm32f417xx electrical characteristics table 21. typical and maximum current consumpt ion in run mode, code with data processing running from flash memory (art accelerator disabled) symbol parameter conditions f hclk typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode external clock (2) , all peripherals enabled (3)(4) 168 mhz 93 109 117 ma 144 mhz 76 89 96 120 mhz 67 79 86 90 mhz 53 65 73 60 mhz 37 49 56 30 mhz 20 32 39 25 mhz 16 27 35 16 mhz 11 23 30 8 mhz 6 18 25 4 mhz 4 16 23 2 mhz 3 15 22 external clock (2) , all peripherals disabled (3)(4) 168 mhz 46 61 69 144 mhz 40 52 60 120 mhz 37 48 56 90 mhz 30 42 50 60 mhz 22 33 41 30 mhz 12 24 31 25 mhz 10 21 29 16 mhz 7 19 26 8 mhz 4 16 23 4 mhz 3 15 22 2 mhz 2 14 21 1. based on characterization, tested in production at v dd max and f hclk max with peripherals enabled. 2. external clock is 4 mhz and pll is on when f hclk > 25 mhz. 3. when analog peripheral blocks such as (adcs, dacs, hse, lse, hsi,lsi) are on, an additional power consumption should be considered. 4. when the adc is on (adon bit set in the adc_cr2 regi ster), add an additional power consumption of 1.6 ma per adc for the analog part.
electrical characteristics stm32f415xx, stm32f417xx 86/186 docid022063 rev 4 figure 24. typical current consumption versu s temperature, run mode, code with data processing running from flash (art accelerator on) or ram, and peripherals off figure 25. typical current consumption versu s temperature, run mode, code with data processing running from flash (art accelerator on) or ram, and peripherals on ms19974v1 0 5 10 15 20 25 30 35 40 45 50 0 20 40 60 80 100 120 140 160 180 i dd run (ma) cpu frequency (mh z -45 c 0 c 25 c 55 c 85 c 105 c ms19975v1 0 10 20 30 40 50 60 70 80 90 100 0 20 40 60 80 100 120 140 160 180 i dd run (ma) cpu frequency (mh z -45c 0c 25c 55c 85c 105c
docid022063 rev 4 87/186 stm32f415xx, stm32f417xx electrical characteristics figure 26. typical current consumption versu s temperature, run mode, code with data processing running from flash (art accelerator off) or ram, and peripherals off figure 27. typical current consumption versu s temperature, run mode, code with data processing running from flash (art acceler ator off) or ram, and peripherals on ms19976v1 0 10 20 30 40 50 60 0 20 40 60 80 100 120 140 160 180 i dd run (ma) cpu frequency (mh z -45c 0c 25c 55c 85c 105c ms19977v1 0 20 40 60 80 100 120 0 20 40 60 80 100 120 140 160 180 i dd run (ma) cpu frequency (mh z -45c 0c 25c 55c 85c 105c
electrical characteristics stm32f415xx, stm32f417xx 88/186 docid022063 rev 4 table 22. typical and maximum current consumption in sleep mode symbol parameter conditions f hclk typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in sleep mode external clock (2) , all peripherals enabled (3) 168 mhz 59 77 84 ma 144 mhz 46 61 67 120 mhz 38 53 60 90 mhz 30 44 51 60 mhz 20 34 41 30 mhz 11 24 31 25 mhz 8 21 28 16 mhz 6 18 25 8 mhz 3 16 23 4 mhz 2 15 22 2 mhz 2 14 21 external clock (2) , all peripherals disabled 168 mhz 12 27 35 144 mhz 9 22 29 120 mhz 8 20 28 90 mhz 7 19 26 60 mhz 5 17 24 30 mhz 3 16 23 25 mhz 2 15 22 16 mhz 2 14 21 8 mhz 1 14 21 4 mhz 1 13 21 2 mhz 1 13 21 1. based on characterization, tested in production at v dd max and f hclk max with peripherals enabled. 2. external clock is 4 mhz and pll is on when f hclk > 25 mhz. 3. add an additional power consumption of 1.6 ma per adc for th e analog part. in applications, th is consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register).
docid022063 rev 4 89/186 stm32f415xx, stm32f417xx electrical characteristics table 23. typical and maximum current consumptions in stop mode symbol parameter conditions typ max unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c i dd_stop supply current in stop mode with main regulator in run mode flash in stop mode, low-speed and high- speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 0.45 1.5 11.00 20.00 ma flash in deep power down mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 0.40 1.5 11.00 20.00 supply current in stop mode with main regulator in low power mode flash in stop mode, low-speed and high- speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 0.31 1.1 8.00 15.00 flash in deep power down mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 0.28 1.1 8.00 15.00 table 24. typical and maximum current consumptions in standby mode symbol parameter conditions typ max (1) unit t a = 25 c t a = 85 c t a = 105 c v dd = 1.8 v v dd = 2.4 v v dd = 3.3 v v dd = 3.6 v i dd_stby supply current in standby mode backup sram on, low- speed oscillator and rtc on 3.0 3.4 4.0 20 36 a backup sram off, low- speed oscillator and rtc on 2.4 2.7 3.3 16 32 backup sram on, rtc off 2.4 2.6 3.0 12.5 24.8 backup sram off, rtc off 1.7 1.9 2.2 9.8 19.2 1. based on characterization, not tested in production.
electrical characteristics stm32f415xx, stm32f417xx 90/186 docid022063 rev 4 figure 28. typical v bat current consumption (lse and rtc on/backup ram off) table 25. typical and maximum current consumptions in v bat mode symbol parameter conditions typ max (1) unit t a = 25 c t a = 85 c t a = 105 c v bat = 1.8 v v bat = 2.4 v v bat = 3.3 v v bat = 3.6 v i dd_vba t backup domain supply current backup sram on, low-speed oscillator and rtc on 1.29 1.42 1.68 6 11 a backup sram off, low-speed oscillator and rtc on 0.62 0.73 0.96 3 5 backup sram on, rtc off 0.79 0.81 0.86 5 10 backup sram off, rtc off 0.10 0.10 0.10 2 4 1. based on characterization, not tested in production. ms19990v1 0 0.5 1 1.5 2 2.5 3 3.5 0 102030405060708090100 ivbat in (a) te m p e r a t u r e i n ( c ) 1.65v 1.8v 2v 2.4v 2.7v 3v 3.3v 3.6v
docid022063 rev 4 91/186 stm32f415xx, stm32f417xx electrical characteristics figure 29. typical v bat current consumption (lse and rtc on/backup ram on) i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up ge nerate current consumpt ion when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resi stors values given in table 47: i/o static characteristics . for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applie d. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input va lue. unless this spec ific configuration is required by the application, this supply curr ent consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an in termediate voltage level or switch inadvertently, as a result of external electromagnetic nois e. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by usin g pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption measured previously (see table 27: peripheral current consumption ), the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the mcu ms19991v1 0 1 2 3 4 5 6 0 102030405060708090100 ivbat in (a) te m p e r a t u r e i n ( c ) 1.65v 1.8v 2v 2.4v 2.7v 3v 3.3v 3.6v
electrical characteristics stm32f415xx, stm32f417xx 92/186 docid022063 rev 4 supply voltage to supply the i/o pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: where i sw is the current sunk by a switching i/ o to charge/discharge the capacitive load v dd is the mcu supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. i sw v dd f sw c =
docid022063 rev 4 93/186 stm32f415xx, stm32f417xx electrical characteristics table 26. switching output i/o current consumption symbol parameter conditions (1) i/o toggling frequency (f sw ) typ unit i ddio i/o switching current v dd = 3.3 v (2) c = c int 2 mhz 0.02 ma 8 mhz 0.14 25 mhz 0.51 50 mhz 0.86 60 mhz 1.30 v dd = 3.3 v c ext = 0 pf c = c int + c ext + c s 2 mhz 0.10 8 mhz 0.38 25 mhz 1.18 50 mhz 2.47 60 mhz 2.86 v dd = 3.3 v c ext = 10 pf c = c int + c ext + c s 2 mhz 0.17 8 mhz 0.66 25 mhz 1.70 50 mhz 2.65 60 mhz 3.48 v dd = 3.3 v c ext = 22 pf c = c int + c ext + c s 2 mhz 0.23 8 mhz 0.95 25 mhz 3.20 50 mhz 4.69 60 mhz 8.06 v dd = 3.3 v c ext = 33 pf c = c int + c ext + c s 2 mhz 0.30 8 mhz 1.22 25 mhz 3.90 50 mhz 8.82 60 mhz - (3) 1. c s is the pcb board capacitance including the pad pin. c s = 7 pf (estimated value). 2. this test is performed by cutting the lqfp package pin (pad removal). 3. at 60 mhz, c maximum load is specified 30 pf.
electrical characteristics stm32f415xx, stm32f417xx 94/186 docid022063 rev 4 on-chip peripheral current consumption the current consumption of the on -chip peripherals is given in table 27 . the mcu is placed under the following conditions: ? at startup, all i/o pins are configured as analog pins by firmware. ? all peripherals are disabled unless otherwise mentioned ? the code is running from flash memory and t he flash memory access time is equal to 5 wait states at 168 mhz. ? the code is running from flash memory and t he flash memory access time is equal to 4 wait states at 144 mhz, and the power scale mode is set to 2. ? art accelerator and cache off. ? the given value is calculated by measur ing the difference of current consumption ? with all peripherals clocked off ? with one peripheral clocked on (with only the clock applied) ? when the peripherals are enabled: hclk is the system clock, f pclk1 = f hclk /4, and f pclk2 =f hclk /2. ? the typical values are obtained for v dd = 3.3 v and t a = 25 c, unless otherwise specified. table 27. peripheral current consumption peripheral (1) 168 mhz 144 mhz unit ahb1 gpio a 0.49 0.36 ma gpio b 0.45 0.33 gpio c 0.45 0.34 gpio d 0.45 0.34 gpio e 0.47 0.35 gpio f 0.45 0.33 gpio g 0.44 0.33 gpio h 0.45 0.34 gpio i 0.44 0.33 otg_hs + ulpi 4.57 3.55 crc 0.07 0.06 bkpsram 0.11 0.08 dma1 6.15 4.75 dma2 6.24 4.8 eth_mac + eth_mac_tx eth_mac_rx eth_mac_ptp 3.28 2.54 ahb2 otg_fs 4.59 3.69 ma dcmi 1.04 0.80
docid022063 rev 4 95/186 stm32f415xx, stm32f417xx electrical characteristics ahb2 rng 0.29 0.23 ma hash 1.71 1.31 crypto 0.41 0.31 ahb3 fsmc 2.18 1.67 ma apb1 tim2 0.80 0.61 tim3 0.58 0.44 tim4 0.62 0.48 tim5 0.79 0.61 tim6 0.15 0.11 tim7 0.16 0.12 tim12 0.33 0.26 tim13 0.27 0.21 tim14 0.27 0.21 pwr 0.04 0.03 usart2 0.17 0.13 usart3 0.17 0.13 uart4 0.17 0.13 uart5 0.17 0.13 i2c1 0.17 0.13 i2c2 0.18 0.13 i2c3 0.18 0.13 spi2/i2s2 (2) 0.17/0.16 0.13/0.12 spi3/i2s3 (2) 0.16/0.14 0.12/0.12 can1 0.27 0.21 can2 0.26 0.20 dac 0.14 0.10 dac channel 1 (3) 0.91 0.89 dac channel 2 (4) 0.91 0.89 dac channel 1 and 2 (3)(4) 1.69 1.68 wwdg 0.04 0.04 table 27. peripheral current consumption (continued) peripheral (1) 168 mhz 144 mhz unit
electrical characteristics stm32f415xx, stm32f417xx 96/186 docid022063 rev 4 5.3.7 wakeup time from low-power mode the wakeup times given in table 28 is measured on a wakeup phase with a 16 mhz hsi rc oscillator. the clock source used to wake up the device depends from the current operating mode: ? stop or standby mode: the clo ck source is the rc oscillator ? sleep mode: the clock source is the clock that was set before entering sleep mode. all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 14 . apb2 sdio 0.64 0.54 ma tim1 1.47 1.14 tim8 1.58 1.22 tim9 0.68 0.54 tim10 0.45 0.36 tim11 0.47 0.38 adc1 (5) 2.20 2.10 adc2 (5) 2.04 1.93 adc3 (5) 2.10 2.00 spi1 0.14 0.12 usart1 0.34 0.27 usart6 0.34 0.28 1. hse oscillator with 4 mhz crystal and pll are on. 2. i2smod bit set in spi_i2scfgr register, and then the i2se bit set to enable i 2 s peripheral. 3. en1 bit is set in dac_cr register. 4. en2 bit is set in dac_cr register. 5. adon bit set in adc_cr2 register. table 27. peripheral current consumption (continued) peripheral (1) 168 mhz 144 mhz unit table 28. low-power mode wakeup timings symbol parameter min (1) typ (1) max (1) unit t wusleep (2) wakeup from sleep mode - 1 - s t wustop (2) wakeup from stop mode (regulator in run mode) - 13 - s wakeup from stop mode (regulator in low power mode) - 17 40 wakeup from stop mode (regulator in low power mode and flash memory in deep power down mode) -110- t wustdby (2)(3) wakeup from standby mode 260 375 480 s 1. based on characterization, not tested in production. 2. the wakeup times are measured from the wakeup event to the point in which the application c ode reads the first instruction. 3. t wustdby minimum and maximum values are give n at 105 c and ?45 c, respectively.
docid022063 rev 4 97/186 stm32f415xx, stm32f417xx electrical characteristics 5.3.8 external clock source characteristics high-speed external user clock generated from an external source the characteristics given in table 29 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in table 14 . low-speed external user clock generated from an external source the characteristics given in table 30 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in table 14 . table 29. high-speed external user clock characteristics symbol parameter conditions min typ max unit f hse_ext external user clock source frequency (1) 1-50mhz v hseh osc_in input pin high level voltage 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss -0.3v dd t w(hse) t w(hse) osc_in high or low time (1) 1. guaranteed by design, not tested in production. 5-- ns t r(hse) t f(hse) osc_in rise or fall time (1) --10 c in(hse) osc_in input capacitance (1) -5-pf ducy (hse) duty cycle 45 - 55 % i l osc_in input leakage current v ss v in v dd --1a table 30. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss -0.3v dd t w(lse) t f(lse) osc32_in high or low time (1) 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time (1) --50 c in(lse) osc32_in input capacitance (1) -5-pf ducy (lse) duty cycle 30 - 70 % i l osc32_in input leakage current v ss v in v dd --1a 1. guaranteed by design, not tested in production.
electrical characteristics stm32f415xx, stm32f417xx 98/186 docid022063 rev 4 figure 30. high-speed external clock source ac timing diagram figure 31. low-speed external clock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 26 mhz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 31 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). ai17528 os c _i n external stm32f clock source v hseh t f(hse) t w(hse) i l 90% 10% t hse t t r(hse) t w(hse) f hse_ext v hsel ai17529 osc32_in external stm32f clock source v lseh t f(lse) t w(lse) i l 90% 10% t lse t t r(lse) t w(lse) f lse_ext v lsel
docid022063 rev 4 99/186 stm32f415xx, stm32f417xx electrical characteristics for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high- frequency applications, and selected to match the requirements of the crystal or resonator (see figure 32 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . note: for information on electing the crystal, refer to the app lication note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. figure 32. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 32 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). table 31. hse 4-26 mhz oscillator characteristics (1) (2) 1. resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. based on characterization, not tested in production. symbol parameter conditions min typ max unit f osc_in oscillator frequency 4 - 26 mhz r f feedback resistor - 200 - k i dd hse current consumption v dd =3.3 v, esr= 30 ? , c l =5 pf@25 mhz -449- a v dd =3.3 v, esr= 30 ? , c l =10 pf@25 mhz -532- g m oscillator transconductance startup 5 - - ma/v t su(hse (3) 3. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer startup time v dd is stabilized - 2 - ms ai17530 osc_ou t osc_in f hse c l1 r f stm32f 8 mh z resonator resonator with integrated capacitors bias controlled gain r ext (1) c l2
electrical characteristics stm32f415xx, stm32f417xx 100/186 docid022063 rev 4 note: for information on electing the crystal, refer to the app lication note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. figure 33. typical applicati on with a 32.768 khz crystal 5.3.9 internal clock source characteristics the parameters given in table 33 and table 34 are derived from tests performed under ambient temperature and v dd supply voltage condit ions summarized in table 14 . high-speed internal (hsi) rc oscillator table 32. lse oscillator characteristics (f lse = 32.768 khz) (1) 1. guaranteed by design, not tested in production. symbol parameter conditions min typ max unit r f feedback resistor - 18.4 - m i dd lse current consumption - - 1 a g m oscillator transconductance 2.8 - - a/v t su(lse) (2) 2. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is m easured for a standard crystal resonator and it can vary significantly with t he crystal manufacturer startup time v dd is stabilized - 2 - s ai17531 osc32_ou t osc32_in f lse c l1 r f stm32f 32.768 kh z resonator resonator with integrated capacitors bias controlled gain c l2 table 33. hsi oscillator characteristics (1) symbol parameter conditions min typ max unit f hsi frequency - 16 - mhz acc hsi accuracy of the hsi oscillator user-trimmed with the rcc_cr register --1% factory- calibrated t a = ?40 to 105 c (2) ?8 - 4.5 % t a = ?10 to 85 c (2) ?4 - 4 % t a = 25 c ?1 - 1 % t su(hsi) (3) hsi oscillator startup time -2.24 s i dd(hsi) hsi oscillator power consumption -6080a
docid022063 rev 4 101/186 stm32f415xx, stm32f417xx electrical characteristics low-speed internal (lsi) rc oscillator figure 34. acc lsi versus temperature 5.3.10 pll characteristics the parameters given in table 35 and table 36 are derived from tests performed under temperature and v dd supply voltage conditions summarized in table 14 . 1. v dd = 3.3 v, t a = ?40 to 105 c unless otherwise specified. 2. based on characterization, not tested in production. 3. guaranteed by design, not tested in production. table 34. lsi oscillator characteristics (1) 1. v dd = 3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi (2) 2. based on characterization, not tested in production. frequency 17 32 47 khz t su(lsi) (3) 3. guaranteed by design, not tested in production. lsi oscillator startup time - 15 40 s i dd(lsi) (3) lsi oscillator power consumption - 0.4 0.6 a ms19013v1 -40 -30 -20 -10 0 10 20 30 40 50 -45-35-25-15-5 5 152535455565758595105 nor m ali zed devi ati on (%) temperat ure (c) max avg min
electrical characteristics stm32f415xx, stm32f417xx 102/186 docid022063 rev 4 table 35. main pll characteristics symbol parameter conditions min typ max unit f pll_in pll input clock (1) 0.95 (2) 12.10mhz f pll_out pll multiplier output clock 24 - 168 mhz f pll48_out 48 mhz pll multiplier output clock -48 75mhz f vco_out pll vco output 192 - 432 mhz t lock pll lock time vco freq = 192 mhz 75 - 200 s vco freq = 432 mhz 100 - 300 jitter (3) cycle-to-cycle jitter system clock 120 mhz rms - 25 - ps peak to peak - 150 - period jitter rms - 15 - peak to peak - 200 - main clock output (mco) for rmii ethernet cycle to cycle at 50 mhz on 1000 samples -32 - main clock output (mco) for mii ethernet cycle to cycle at 25 mhz on 1000 samples -40 - bit time can jitter cycle to cycle at 1 mhz on 1000 samples - 330 - i dd(pll) (4) pll power consumption on vdd vco freq = 192 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(pll) (4) pll power consumption on vdda vco freq = 192 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 ma 1. take care of using the appropriate division factor m to obtai n the specified pll input clock values. the m factor is shared between pll and plli2s. 2. guaranteed by design, not tested in production. 3. the use of 2 plls in parallel could degraded the jitter up to +30%. 4. based on characterization, not tested in production. table 36. plli2s (audio pll) characteristics symbol parameter conditions min typ max unit f plli2s_in plli2s input clock (1) 0.95 (2) 12.10mhz f plli2s_out plli2s multiplier output clock - - 216 mhz f vco_out plli2s vco output 192 - 432 mhz t lock plli2s lock time vco freq = 192 mhz 75 - 200 s vco freq = 432 mhz 100 - 300
docid022063 rev 4 103/186 stm32f415xx, stm32f417xx electrical characteristics 5.3.11 pll spread spectrum clo ck generation (sscg) characteristics the spread spectrum clock generation (sscg) feature allows to reduce electromagnetic interferences (see table 43: emi characteristics ). it is available only on the main pll. equation 1 the frequency modulation period (modeper) is given by the equation below: f pll_in and f mod must be expressed in hz. as an example: if f pll_in = 1 mhz, and f mod = 1 khz, the modulation dep th (modeper) is given by equation 1: jitter (3) master i 2 s clock jitter cycle to cycle at 12.288 mhz on 48khz period, n=432, r=5 rms - 90 - peak to peak - 280 - ps average frequency of 12.288 mhz n = 432, r = 5 on 1000 samples -90 -ps ws i 2 s clock jitter cycle to cycle at 48 khz on 1000 samples -400 - ps i dd(plli2s) (4) plli2s power consumption on v dd vco freq = 192 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(plli2s) (4) plli2s power consumption on v dda vco freq = 192 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 ma 1. take care of using the appropriate division fact or m to have the specifie d pll input clock values. 2. guaranteed by design, not tested in production. 3. value given with main pll running. 4. based on characterization, not tested in production. table 36. plli2s (audio pll) characteristics (continued) symbol parameter conditions min typ max unit table 37. sscg parameters constraint symbol parameter min typ max (1) unit f mod modulation frequency - - 10 khz md peak modulation depth 0.25 - 2 % modeper * incstep - - 2 15 ? 1- 1. guaranteed by design, not tested in production. modeper round f pll_in 4f mod () ? [] = modeper round 10 6 410 3 () ? [] 250 ==
electrical characteristics stm32f415xx, stm32f417xx 104/186 docid022063 rev 4 equation 2 equation 2 allows to calculate the increment step (incstep): f vco_out must be expressed in mhz. with a modulation depth (md) = 2 % (4 % peak to peak), and plln = 240 (in mhz): an amplitude quantization error may be generat ed because the linear modulation profile is obtained by taking the quantized values (roun ded to the nearest integer) of modper and incstep. as a result, the achieved modulation depth is quantized. the percentage quantized modulation depth is given by the following formula: as a result: figure 35 and figure 36 show the main pll output clock waveforms in center spread and down spread modes, where: f0 is f pll_out nominal. t mode is the modulation period. md is the modulation depth. figure 35. pll output clock waveforms in center spread mode incstep round 2 15 1 ? () md plln () 100 5 modeper () ? [] = incstep round 2 15 1 ? () 2 240 () 100 5 250 () ? [] 126md(quantitazed)% == md quantized % modeper incstep 100 5 () 2 15 1 ? () plln () ? = md quantized %250126 100 5 () 2 15 1 ? () 240 () ? 2.002%(peak) == frequency (pll_out) time f0 tmode md ai17291 md 2 x tmode
docid022063 rev 4 105/186 stm32f415xx, stm32f417xx electrical characteristics figure 36. pll output clock waveforms in down spread mode 5.3.12 memory characteristics flash memory the characteristics are given at t a = ? 40 to 105 c unless otherwise specified. the devices are shipped to customers with the flash memory erased. time ai17292 frequency (pll_out) f0 2 x md tmode 2 x tmode table 38. flash memory characteristics symbol parameter conditions min typ max unit i dd supply current write / erase 8-bit mode, v dd = 1.8 v - 5 - ma write / erase 16-bit mode, v dd = 2.1 v - 8 - write / erase 32-bit mode, v dd = 3.3 v - 12 - table 39. flash memory programming symbol parameter conditions min (1) typ max (1) unit t prog word programming time program/erase parallelism (psize) = x 8/16/32 -16100 (2) s t erase16kb sector (16 kb) erase time program/erase parallelism (psize) = x 8 - 400 800 ms program/erase parallelism (psize) = x 16 - 300 600 program/erase parallelism (psize) = x 32 - 250 500
electrical characteristics stm32f415xx, stm32f417xx 106/186 docid022063 rev 4 t erase64kb sector (64 kb) erase time program/erase parallelism (psize) = x 8 - 1200 2400 ms program/erase parallelism (psize) = x 16 - 700 1400 program/erase parallelism (psize) = x 32 - 550 1100 t erase128kb sector (128 kb) erase time program/erase parallelism (psize) = x 8 -24 s program/erase parallelism (psize) = x 16 -1.32.6 program/erase parallelism (psize) = x 32 -12 t me mass erase time program/erase parallelism (psize) = x 8 -1632 s program/erase parallelism (psize) = x 16 -1122 program/erase parallelism (psize) = x 32 -816 v prog programming voltage 32-bit program operation 2.7 - 3.6 v 16-bit program operation 2.1 - 3.6 v 8-bit program operation 1.8 - 3.6 v 1. based on characterization, not tested in production. 2. the maximum programming time is m easured after 100k erase operations. table 39. flash memory programming (continued) symbol parameter conditions min (1) typ max (1) unit
docid022063 rev 4 107/186 stm32f415xx, stm32f417xx electrical characteristics 5.3.13 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (p ositive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. table 40. flash memory programming with v pp symbol parameter conditions min (1) typ max (1) 1. guaranteed by design, not tested in production. unit t prog double word programming t a = 0 to +40 c v dd = 3.3 v v pp = 8.5 v -16100 (2) 2. the maximum programming time is measured after 100k erase operations. s t erase16kb sector (16 kb) erase time - 230 - ms t erase64kb sector (64 kb) erase time - 490 - t erase128kb sector (128 kb) erase time - 875 - t me mass erase time - 6.9 - s v prog programming voltage 2.7 - 3.6 v v pp v pp voltage range 7 - 9 v i pp minimum current sunk on the v pp pin 10 - - ma t vpp (3) 3. v pp should only be connected during programming/erasing. cumulative time during which v pp is applied --1hour table 41. flash memory endurance and data retention symbol parameter conditions value unit min (1) 1. based on characterization, not tested in production. n end endurance t a = ?40 to +85 c (6 suffix versions) t a = ?40 to +105 c (7 suffix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over the whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20
electrical characteristics stm32f415xx, stm32f417xx 108/186 docid022063 rev 4 a device reset allows normal operations to be resumed. the test results are given in table 42 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application, executing eembc ? code, is running. this emission test is compliant with sae iec61967-2 standard which specifies the test board and the pin loading. table 42. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp176, t a = +25 c, f hclk = 168 mhz, conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, lqfp176, t a = +25 c, f hclk = 168 mhz, conforms to iec 61000-4-2 4a
docid022063 rev 4 109/186 stm32f415xx, stm32f417xx electrical characteristics 5.3.14 absolute maximum ratings (electrical sensitivity) based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. static latchup two complementary static te sts are required on six pa rts to assess the latchup performance: ? a supply overvoltage is applied to each power supply pin ? a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latchup standard. table 43. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f cpu ] unit 25/168 mhz s emi peak level v dd = 3.3 v, t a = 25 c, lqfp176 package, conforming to sae j1752/3 eembc, code running from flash with art accelerator enabled 0.1 to 30 mhz 32 dbv 30 to 130 mhz 25 130 mhz to 1ghz 29 sae emi level 4 - v dd = 3.3 v, t a = 25 c, lqfp176 package, conforming to sae j1752/3 eembc, code running from flash with art accelerator and pll spread spectrum enabled 0.1 to 30 mhz 19 dbv 30 to 130 mhz 16 130 mhz to 1ghz 18 sae emi level 3.5 - table 44. esd absolute maximum ratings symbol ratings conditions class maximum value (1) unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c conforming to jesd22-a114 2 2000 (2) v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c conforming to jesd22-c101 ii 500 1. based on characterization results, not tested in production. 2. on v bat pin, v esd(hbm) is limited to 1000 v.
electrical characteristics stm32f415xx, stm32f417xx 110/186 docid022063 rev 4 5.3.15 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indica tion of the robustness of the microcontroller in cases when abnormal injection ac cidentally happens, susceptib ility tests are pe rformed on a sample basis during device characterization. functional susceptibilty to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (>5 lsb tue), out of conventional limits of induc ed leakage current on adjacent pins (out of 5 ua/+0 ua range), or other functional failu re (for example reset, oscillator frequency deviation). negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. the test results are given in table 46 . 5.3.16 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 47 are derived from tests performed under the conditions summarized in table 14 . all i/os are cmos and ttl compliant. table 45. electric al sensitivities symbol parameter c onditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a table 46. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj (1) 1. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. injected current on all ft pins ?5 +0 ma injected current on any other pin ?5 +5
docid022063 rev 4 111/186 stm32f415xx, stm32f417xx electrical characteristics all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. output driving current the gpios (general purpose input/outputs) can sink or source up to 8 ma, and sink or source up to 20 ma (with a relaxed v ol /v oh ) except pc13, pc14 and pc15 which can sink or source up to 3ma. when using the pc13 to pc15 gpios in output mode, the speed should not exceed 2 mhz with a maximum load of 30 pf. table 47. i/o static characteristics symbol parameter conditions min typ max unit v il input low level voltage ttl ports 2.7 v v dd 3.6 v --0.8 v v ih (1) input high level voltage 2.0 - - v il input low level voltage cmos ports 1.8 v v dd 3.6 v - - 0.3v dd v ih (1) input high level voltage 0.7v dd -- -- v hys i/o schmitt trigger voltage hysteresis (2) -200- mv io ft schmitt trigger voltage hysteresis (2) 5% v dd (3) -- i lkg i/o input leakage current (4) v ss v in v dd -- 1 a i/o ft input leakage current (4) v in = 5v - - 3 r pu weak pull-up equivalent resistor (5) all pins except for pa10 and pb12 v in = v ss 30 40 50 k pa10 and pb12 81115 r pd weak pull-down equivalent resistor all pins except for pa10 and pb12 v in = v dd 30 40 50 pa10 and pb12 81115 c io (6) i/o pin capacitance 5 pf 1. tested in production. 2. hysteresis voltage between schmitt trigger switching levels . based on characterization, not tested in production. 3. with a minimum of 100 mv. 4. leakage could be higher than the maximum value, if negative current is inje cted on adjacent pins. 5. pull-up and pull-down resistors are desi gned with a true resistance in series with a switchable pmos/nmos. this mos/nmos contribution to the series resistance is minimum (~10% order) . 6. guaranteed by design, not tested in production.
electrical characteristics stm32f415xx, stm32f417xx 112/186 docid022063 rev 4 in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 5.2 . in particular: ? the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see table 12 ). ? the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see table 12 ). output voltage levels unless otherwise specified, the parameters given in table 48 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 14 . all i/os are cmos and ttl compliant. input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 37 and table 49 , respectively. table 48. output voltage characteristics (1) 1. pc13, pc14, pc15 and pi8 are supplied through the power switch. since the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 and pi8 in output mode is limited: the speed should not exceed 2 mhz with a maximum load of 30 pf and these i/os must not be used as a current source (e.g. to drive an led). symbol parameter conditions min max unit v ol (2) 2. the i io current sunk by the device must always re spect the absolute maximu m rating specified in table 12 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin when 8 pins are sunk at same time cmos port i io = +8 ma 2.7 v < v dd < 3.6 v -0.4 v v oh (3) 3. the i io current sourced by the device must always re spect the absolute maximu m rating specified in table 12 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?0.4 - v ol (2) output low level voltage for an i/o pin when 8 pins are sunk at same time ttl port i io =+ 8ma 2.7 v < v dd < 3.6 v -0.4 v v oh (3) output high level voltage for an i/o pin when 8 pins are sourced at same time 2.4 - v ol (2)(4) 4. based on characterization data, not tested in production. output low level voltage for an i/o pin when 8 pins are sunk at same time i io = +20 ma 2.7 v < v dd < 3.6 v -1.3 v v oh (3)(4) output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?1.3 - v ol (2)(4) output low level voltage for an i/o pin when 8 pins are sunk at same time i io = +6 ma 2 v < v dd < 2.7 v -0.4 v v oh (3)(4) output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?0.4 -
docid022063 rev 4 113/186 stm32f415xx, stm32f417xx electrical characteristics unless otherwise specified, the parameters given in table 49 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in table 14 . table 49. i/o ac characteristics (1)(2)(3) ospeedry [1:0] bit value (1) symbol parameter conditions min typ max unit 00 f max(io)out maximum frequency (4) c l = 50 pf, v dd > 2.70 v - - 2 mhz c l = 50 pf, v dd > 1.8 v - - 2 c l = 10 pf, v dd > 2.70 v - - tbd c l = 10 pf, v dd > 1.8 v - - tbd t f(io)out output high to low level fall time c l = 50 pf, v dd = 1.8 v to 3.6 v --tbd ns t r(io)out output low to high level rise time --tbd 01 f max(io)out maximum frequency (4) c l = 50 pf, v dd > 2.70 v - - 25 mhz c l = 50 pf, v dd > 1.8 v - - 12.5 (5) c l = 10 pf, v dd > 2.70 v - - 50 (5) c l = 10 pf, v dd > 1.8 v - - tbd t f(io)out output high to low level fall time c l = 50 pf, v dd < 2.7 v - - tbd ns c l = 10 pf, v dd > 2.7 v - - tbd t r(io)out output low to high level rise time c l = 50 pf, v dd < 2.7 v - - tbd c l = 10 pf, v dd > 2.7 v - - tbd 10 f max(io)out maximum frequency (4) c l = 40 pf, v dd > 2.70 v - - 50 (5) mhz c l = 40 pf, v dd > 1.8 v - - 25 c l = 10 pf, v dd > 2.70 v - - 100 (5) c l = 10 pf, v dd > 1.8 v - - tbd t f(io)out output high to low level fall time c l = 50 pf, 2.4 < v dd < 2.7 v --tbd ns c l = 10 pf, v dd > 2.7 v - - tbd t r(io)out output low to high level rise time c l = 50 pf, 2.4 < v dd < 2.7 v --tbd c l = 10 pf, v dd > 2.7 v - - tbd
electrical characteristics stm32f415xx, stm32f417xx 114/186 docid022063 rev 4 figure 37. i/o ac charac teristics definition 5.3.17 nrst pin characteristics the nrst pin input driver uses cmos technology. it is connected to a permanent pull-up resistor, r pu (see table 47 ). unless otherwise specified, the parameters given in table 50 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in table 14 . 11 f max(io)ou t maximum frequency (4) c l = 30 pf, v dd > 2.70 v - - 100 (5) mhz c l = 30 pf, v dd > 1.8 v - - 50 (5) c l = 10 pf, v dd > 2.70 v - - 200 (5) c l = 10 pf, v dd > 1.8 v - - tbd t f(io)out output high to low level fall time c l = 20 pf, 2.4 < v dd < 2.7 v --tbd ns c l = 10 pf, v dd > 2.7 v - - tbd t r(io)out output low to high level rise time c l = 20 pf, 2.4 < v dd < 2.7 v --tbd c l = 10 pf, v dd > 2.7 v - - tbd -t extipw pulse width of external signals detected by the exti controller 10 - - ns 1. based on characterization data, not tested in production. 2. the i/o speed is configured using th e ospeedry[1:0] bits. refer to the st m32f20/21xxx reference manual for a description of the gpiox_speedr gpio port output speed register. 3. tbd stands for ?to be defined?. 4. the maximum frequency is defined in figure 37 . 5. for maximum frequencies above 50 mhz, the compensation cell should be used. table 49. i/o ac characteristics (1)(2)(3) (continued) ospeedry [1:0] bit value (1) symbol parameter conditions min typ max unit ai14131 10% 90% 50% t r(io)out output external on 50pf maximum frequency is achieved if (t r + t f ) 2/3)t and if the duty cycle is (45-55%) 10% 50% 90% when loaded by 50pf t t r(io)out
docid022063 rev 4 115/186 stm32f415xx, stm32f417xx electrical characteristics figure 38. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 50 . otherwise the reset is not taken into account by the device. 5.3.18 tim time r characteristics the parameters given in table 51 and table 52 are guaranteed by design. refer to section 5.3.16: i/o port characteristics for details on the input/output alternate function characteristics (output compare, i nput capture, external clock, pwm output). table 50. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) 1. guaranteed by design, not tested in production. nrst input low level voltage ttl ports 2.7 v v dd 3.6 v --0.8 v v ih(nrst) (1) nrst input high level voltage 2 - - v il(nrst) (1) nrst input low level voltage cmos ports 1.8 v v dd 3.6 v -0.3v dd v ih(nrst) (1) nrst input high level voltage 0.7v dd - v hys(nrst) nrst schmitt trigger voltage hysteresis -200 - mv r pu weak pull-up equivalent resistor (2) 2. the pull-up is designed with a true resistance in seri es with a switchable pmos. this pmos contribution to the series resistance must be minimum (~10% order) . v in = v ss 30 40 50 k v f(nrst) (1) nrst input filtered pulse - - 100 ns v nf(nrst) (1) nrst input not filtered pulse v dd > 2.7 v 300 - - ns t nrst_out generated reset pulse duration internal reset source 20 - - s ai14132c stm32fxxx r pu nrst (2) v dd filter internal reset 0.1 f external reset circuit (1)
electrical characteristics stm32f415xx, stm32f417xx 116/186 docid022063 rev 4 table 51. characteristics of timx connected to the apb1 domain (1) 1. timx is used as a general term to refer to the tim2, tim3, tim4, tim5, tim6, tim7, and tim12 timers. symbol parameter conditions min max unit t res(tim) timer resolution time ahb/apb1 prescaler distinct from 1, f timxclk = 84 mhz 1-t timxclk 11.9 - ns ahb/apb1 prescaler = 1, f timxclk = 42 mhz 1-t timxclk 23.8 - ns f ext timer external clock frequency on ch1 to ch4 f timxclk = 84 mhz apb1= 42 mhz 0f timxclk /2 mhz 042mhz res tim timer resolution - 16/32 bit t counter 16-bit counter clock period when internal clock is selected 1 65536 t timxclk 0.0119 780 s 32-bit counter clock period when internal clock is selected 1-t timxclk 0.0119 51130563 s t max_count maximum possible count - 65536 65536 t timxclk - 51.1 s
docid022063 rev 4 117/186 stm32f415xx, stm32f417xx electrical characteristics 5.3.19 communications interfaces i 2 c interface characteristics the stm32f415xx and stm32f417xx i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: the i/o pins sda and scl are mapped to are not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in table 53 . refer also to section 5.3.16: i/o port characteristics for more details on the input/output al ternate function characteristics (sda and scl) . table 52. characteristics of timx connected to the apb2 domain (1) 1. timx is used as a general term to refer to the tim1, tim8, tim9, tim10, and tim11 timers. symbol parameter conditions min max unit t res(tim) timer resolution time ahb/apb2 prescaler distinct from 1, f timxclk = 168 mhz 1-t timxclk 5.95 - ns ahb/apb2 prescaler = 1, f timxclk = 84 mhz 1-t timxclk 11.9 - ns f ext timer external clock frequency on ch1 to ch4 f timxclk = 168 mhz apb2 = 84 mhz 0f timxclk /2 mhz 084mhz res tim timer resolution - 16 bit t counter 16-bit counter clock period when internal clock is selected 1 65536 t timxclk t max_count maximum possible count - 32768 t timxclk table 53. i 2 c characteristics symbol parameter standard mode i 2 c (1) fast mode i 2 c (1)(2) unit min max min max t w(scll) scl clock low time 4.7 - 1.3 - s t w(sclh) scl clock high time 4.0 - 0.6 - t su(sda) sda setup time 250 - 100 - ns t h(sda) sda data hold time 0 (3) -0900 (4) t r(sda) t r(scl) sda and scl rise time - 1000 20 + 0.1c b 300 t f(sda) t f(scl) sda and scl fall time - 300 - 300
electrical characteristics stm32f415xx, stm32f417xx 118/186 docid022063 rev 4 figure 39. i 2 c bus ac waveforms and measurement circuit 1. rs= series protection resistor. 2. rp = external pull-up resistor. 3. vdd_i2c is the i2c bus power supply. t h(sta) start condition hold time 4.0 - 0.6 - s t su(sta) repeated start condition setup time 4.7 - 0.6 - t su(sto) stop condition setup time 4.0 - 0.6 - s t w(sto:sta) stop to start condition time (bus free) 4.7 - 1.3 - s c b capacitive load for each bus line - 400 - 400 pf 1. guaranteed by design, not tested in production. 2. f pclk1 must be at least 2 mhz to achieve standard mode i 2 c frequencies. it must be at least 4 mhz to achieve fast mode i 2 c frequencies, and a multiple of 10 mhz to reach the 400 khz maximum i 2 c fast mode clock. 3. the device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined region of the falling edge of scl. 4. the maximum data hold time has only to be met if the interface does not stretch the low period of scl signal. table 53. i 2 c characteristics (continued) symbol parameter standard mode i 2 c (1) fast mode i 2 c (1)(2) unit min max min max ai14979c start sda r p i2c bus v dd_i2c stm32fxx sda scl t f(sda) t r(sda) scl t h(sta) t w(sclh) t w(scll) t su(sda) t r(scl) t f(scl) t h(sda) s t ar t repeated start t su(sta) t su(sto) stop t w(sto:sta) v dd_i2c r p r s r s
docid022063 rev 4 119/186 stm32f415xx, stm32f417xx electrical characteristics spi interface characteristics unless otherwise specified, the parameters given in table 55 for spi are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions su mmarized in table 14 with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5 v dd refer to section 5.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso). table 54. scl frequency (f pclk1 = 42 mhz.,v dd = 3.3 v) (1)(2) 1. r p = external pull-up resistance, f scl = i 2 c speed, 2. for speeds around 200 khz, the tole rance on the achieved speed is of 5%. for other speed ranges, the tolerance on the achieved speed 2%. these variations depend on the accuracy of the external components used to design the application. f scl (khz) i2c_ccr value r p = 4.7 k 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012c 20 0x02ee table 55. spi dynamic characteristics (1) symbol parameter conditions min typ max unit f sck spi clock frequency master mode, spi1, 2.7v < v dd < 3.6v -- 42 mhz slave mode, spi1, 2.7v < v dd < 3.6v 42 1/t c(sck) master mode, spi1/2/3, 1.7v < v dd < 3.6v -- 21 slave mode, spi1/2/3, 1.7v < v dd < 3.6v 21 duty(sck) duty cycle of spi clock frequency slave mode 30 50 70 %
electrical characteristics stm32f415xx, stm32f417xx 120/186 docid022063 rev 4 t w(sckh) sck high and low time master mode, spi presc = 2, 2.7v < v dd < 3.6v t pclk -0.5 t pclk t pclk +0.5 ns t w(sckl) master mode, spi presc = 2, 1.7v < v dd < 3.6v t pclk -2 t pclk t pclk +2 t su(nss) nss setup time slave mode, spi presc = 2 4 x t pclk -- t h(nss) nss hold time slave mode, spi presc = 2 2 x t pclk t su(mi) data input setup time master mode 6.5 - - t su(si) slave mode 2.5 - - t h(mi) data input hold time master mode 2.5 - - t h(si) slave mode 4 - - t a(so) (2) data output access time slave mode, spi presc = 2 0 - 4 x t pclk t dis(so) (3) data output disable time slave mode, spi1, 2.7v < v dd < 3.6v 0-7.5 slave mode, spi1/2/3 1.7v < v dd < 3.6v 0-16.5 t v(so) t h(so) data output valid/hold time slave mode (after enable edge), spi1, 2.7v < v dd < 3.6v -1113 slave mode (after enable edge), spi2/3, 2.7v < v dd < 3.6v -1216.5 slave mode (after enable edge), spi1, 1.7v < v dd < 3.6v - 15.5 19 slave mode (after enable edge), spi2/3, 1.7v < v dd < 3.6v -1820.5 t v(mo) data output valid time master mode (after enable edge), spi1 , 2.7v < v dd < 3.6v --2.5 master mode (after enable edge), spi1/2/3 , 1.7v < v dd < 3.6v --4.5 t h(mo) data output hold time master mode (after enable edge) 0 - - 1. data based on characterization re sults, not tested in production. 2. min time is for the minimum time to drive the output and t he max time is for the maximum time to validate the data. 3. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z. table 55. spi dynamic characteristics (1) (continued) symbol parameter conditions min typ max unit
docid022063 rev 4 121/186 stm32f415xx, stm32f417xx electrical characteristics figure 40. spi timing diagram - slave mode and cpha = 0 figure 41. spi timing diagram - slave mode and cpha = 1 ai14134c sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input
electrical characteristics stm32f415xx, stm32f417xx 122/186 docid022063 rev 4 figure 42. spi timing diagram - master mode ai14136 sck input cpha= 0 mosi outut miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck input cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo)
docid022063 rev 4 123/186 stm32f415xx, stm32f417xx electrical characteristics i 2 s interface characteristics unless otherwise specified, the parameters given in table 56 for the i 2 s interface are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 14 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5 v dd refer to section 5.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (ck, sd, ws). note: refer to the i 2 s section of rm0090 reference manual for more details on the sampling frequency (f s ). f mck , f ck , and d ck values reflect only the digital peripheral behavior. the value of these parameters might be slightly impacted by the source clock accuracy. d ck depends mainly on the value of odd bit. the digital contribution leads to a minimum value of i2sdiv / (2 x i2sdiv + odd) and a maximu m value of (i2sdiv + odd) / (2 x i2sdiv + odd). f s maximum value is supported for each mode/condition. table 56. i 2 s dynamic characteristics (1) symbol parameter conditions min max unit f mck i 2 s main clock output - 256 x 8k 256 x f s (2) mhz f ck i 2 s clock frequency master data: 32 bits - 64 x f s mhz slave data: 32 bits - 64 x f s d ck i 2 s clock frequency duty cycle slave receiver 30 70 % t v(ws) ws valid time master mode 0 6 ns t h(ws) ws hold time master mode 0 - t su(ws) ws setup time slave mode 1 - t h(ws) ws hold time slave mode 0 - t su(sd_mr) data input setup time master receiver 7.5 - t su(sd_sr) slave receiver 2 - t h(sd_mr) data input hold time master receiver 0 - t h(sd_sr) slave receiver 0 - t v(sd_st) t h(sd_st) data output valid time slave transmitter (after enable edge) - 27 t v(sd_mt) master transmitter (after enable edge) - 20 t h(sd_mt) data output hold time master transmitter (after enable edge) 2.5 - 1. data based on characterization re sults, not tested in production. 2. the maximum value of 256 x f s is 42 mhz (apb1 maximum frequency).
electrical characteristics stm32f415xx, stm32f417xx 124/186 docid022063 rev 4 figure 43. i 2 s slave timing diagram (philips protocol) 1. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. figure 44. i 2 s master timing diagram (philips protocol) (1) 1. based on characterization, not tested in production. 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. usb otg fs characteristics this interface is present in both the usb otg hs and usb otg fs controllers. ck inp u t cpol = 0 cpol = 1 t c(ck) w s inp u t s d tr a n s mit s d receive t w(ckh) t w(ckl) t su (w s ) t v( s d_ s t) t h( s d_ s t) t h(w s ) t su ( s d_ s r) t h( s d_ s r) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14881b l s b receive (2) l s b tr a n s mit (2) ck o u tp u t cpol = 0 cpol = 1 t c(ck) w s o u tp u t s d receive s d tr a n s mit t w(ckh) t w(ckl) t su ( s d_mr) t v( s d_mt) t h( s d_mt) t h(w s ) t h( s d_mr) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14884b t f(ck) t r(ck) t v(w s ) l s b receive (2) l s b tr a n s mit (2)
docid022063 rev 4 125/186 stm32f415xx, stm32f417xx electrical characteristics figure 45. usb otg fs timings: definiti on of data signal rise and fall time table 57. usb otg fs startup time symbol parameter max unit t startup (1) 1. guaranteed by design, not tested in production. usb otg fs transceiver startup time 1 s table 58. usb otg fs dc electrical characteristics symbol parameter conditions min. (1) 1. all the voltages are measured from the local ground potential. typ. max. (1) unit input levels v dd usb otg fs operating voltage 3.0 (2) 2. the stm32f415xx and stm32f417xx usb otg fs functional ity is ensured down to 2.7 v but not the full usb otg fs electrical c haracteristics which are degraded in the 2.7-to-3.0 v v dd voltage range. -3.6v v di (3) 3. guaranteed by design, not tested in production. differential input sensitivity i(usb_fs_dp/dm, usb_hs_dp/dm) 0.2 - - v v cm (3) differential common mode range includes v di range 0.8 - 2.5 v se (3) single ended receiver threshold 1.3 - 2.0 output levels v ol static output level low r l of 1.5 k to 3.6 v (4) 4. r l is the load connected on the usb otg fs drivers --0.3 v v oh static output level high r l of 15 k to v ss (4) 2.8 - 3.6 r pd pa11, pa12, pb14, pb15 (usb_fs_dp/dm, usb_hs_dp/dm) v in = v dd 17 21 24 k pa9, pb13 (otg_fs_vbus, otg_hs_vbus) 0.65 1.1 2.0 r pu pa12, pb15 (usb_fs_dp, usb_hs_dp) v in = v ss 1.5 1.8 2.1 pa9, pb13 (otg_fs_vbus, otg_hs_vbus) v in = v ss 0.25 0.37 0.55 ai14137 t f differen tial data l ines v ss v cr s t r crossover points
electrical characteristics stm32f415xx, stm32f417xx 126/186 docid022063 rev 4 usb hs characteristics unless otherwise specified, the parameters given in table 62 for ulpi are derived from tests performed under the ambient temperature, f hclk frequency summarized in table 61 and v dd supply voltage cond itions summarized in table 60 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5v dd . refer to section section 5.3.16: i/o po rt characteristics for more details on the input/outputcharacteristics. table 59. usb otg fs electrical characteristics (1) 1. guaranteed by design, not tested in production. driver characteristics symbol parameter conditions min max unit t r rise time (2) 2. measured from 10% to 90% of the data signal. for more detailed informations, please refer to usb specification - chapter 7 (version 2.0). c l = 50 pf 420ns t f fall time (2) c l = 50 pf 4 20 ns t rfm rise/ fall time matching t r /t f 90 110 % v crs output signal cro ssover voltage 1.3 2.0 v table 60. usb hs dc electrical characteristics symbol parameter min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input level v dd usb otg hs operating voltage 2.7 3.6 v table 61. usb hs clock timing parameters (1) parameter symbol min nominal max unit f hclk value to guarantee proper operation of usb hs interface 30 mhz frequency (first transition) 8-bit 10% f start_8bit 54 60 66 mhz frequency (steady state) 500 ppm f steady 59.97 60 60.03 mhz duty cycle (first transition) 8-bit 10% d start_8bit 40 50 60 % duty cycle (steady state) 500 ppm d steady 49.975 50 50.025 % time to reach the steady state frequency and duty cycle after the first transition t steady --1.4ms clock startup time after the de-assertion of suspendm peripheral t start_dev --5.6 ms host t start_host --- phy preparation time after the first transition of the input clock t prep ---s
docid022063 rev 4 127/186 stm32f415xx, stm32f417xx electrical characteristics figure 46. ulpi timing diagram ethernet characteristics unless otherwise specified, the parameters given in table 64 , table 65 and table 66 for smi, rmii and mii are derived from tests performed under the ambient temperature, f hclk frequency summarized in table 14 and vdd supply voltage conditions summarized in table 63 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5v dd . refer to section 5.3.16: i/o port characteristics for more details on the input/output characteristics. 1. guaranteed by design, not tested in production. table 62. ulpi timing parameter symbol value (1) 1. v dd = 2.7 v to 3.6 v and t a = ?40 to 85 c. unit min. max. control in (ulpi_dir) setup time t sc -2.0 ns control in (ulpi_nxt) setup time - 1.5 control in (ulpi_dir, ulpi_nxt) hold time t hc 0- data in setup time t sd -2.0 data in hold time t hd 0- control out (ulpi_stp) setup time and hold time t dc -9.2 data out available from clock rising edge t dd -10.7 clock control in (ulpi_dir, ulpi_nxt) data in (8-bit) control out (ulpi_stp) data out (8-bit) t dd t dc t hd t sd t hc t sc ai17361c t dc
electrical characteristics stm32f415xx, stm32f417xx 128/186 docid022063 rev 4 table 64 gives the list of ethernet mac signals for the smi (station management interface) and figure 47 shows the corresponding timing diagram. figure 47. ethernet smi timing diagram table 65 gives the list of ethernet mac signals for the rmii and figure 48 shows the corresponding timing diagram. figure 48. ethernet rmii timing diagram table 63. ethernet dc electrical characteristics symbol parameter min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input level v dd ethernet operatin g voltage 2.7 3.6 v table 64. dynamic characteristics: ehternet mac signals for smi (1) 1. data based on characterization results, not tested in production. symbol parameter min typ max unit t mdc mdc cycle time( 2.38 mhz) 411 420 425 ns t d(mdio) write data valid time 6 10 13 t su(mdio) read data setup time 12 - - t h(mdio) read data hold time 0 - - ms31384v1 eth_mdc eth_mdio(o) eth_mdio(i) tmdc td(mdio) tsu(mdio) th(mdio) rmii_ref_clk rmii_tx_en rmii_txd[1:0] rmii_rxd[1:0] rmii_crs_dv t d(txen) t d(txd) t su(rxd) t su(crs) t ih(rxd) t ih(crs) ai15667
docid022063 rev 4 129/186 stm32f415xx, stm32f417xx electrical characteristics table 66 gives the list of ethernet mac signals for mii and figure 48 shows the corresponding timing diagram. figure 49. ethernet mii timing diagram table 65. dynamic characteristics: ethernet mac signals for rmii symbol rating min typ max unit t su(rxd) receive data setup time 2 - - ns t ih(rxd) receive data hold time 1 - - ns t su(crs) carrier sense set-up time 0.5 - - ns t ih(crs) carrier sense hold time 2 - - ns t d(txen) transmit enable valid delay time 8 9.5 11 ns t d(txd) transmit data valid delay time 8.5 10 11.5 ns table 66. dynamic characteristics: ethernet mac signals for mii (1) 1. data based on characterization results, not tested in production. symbol parameter min typ max unit t su(rxd) receive data setup time 9 - ns t ih(rxd) receive data hold time 10 - t su(dv) data valid setup time 9 - t ih(dv) data valid hold time 8 - t su(er) error setup time 6 - t ih(er) error hold time 8 - t d(txen) transmit enable valid delay time 0 10 14 t d(txd) transmit data valid delay time 0 10 15 mii_rx_clk mii_rxd[3:0] mii_rx_dv mii_rx_er t d(txen) t d(txd) t su(rxd) t su(er) t su(dv) t ih(rxd) t ih(er) t ih(dv) ai1566 8 mii_tx_clk mii_tx_en mii_txd[3:0]
electrical characteristics stm32f415xx, stm32f417xx 130/186 docid022063 rev 4 can (controller area network) interface refer to section 5.3.16: i/o port characteristics for more details on the input/output alternate function characteristics (cantx and canrx). 5.3.20 12-bit adc characteristics unless otherwise specified, the parameters given in table 67 are derived from tests performed under the ambient temperature, f pclk2 frequency and v dda supply voltage conditions su mmarized in table 14 . table 67. adc characteristics symbol parameter conditions min typ max unit v dda power supply 1.8 (1) -3.6v v ref+ positive reference voltage 1.8 (1)(2)(3) -v dda v f adc adc clock frequency v dda = 1.8 (1)(3) to 2.4 v 0.6 15 18 mhz v dda = 2.4 to 3.6 v (3) 0.6 30 36 mhz f trig (4) external trigger frequency f adc = 30 mhz, 12-bit resolution - - 1764 khz - - 17 1/f adc v ain conversion voltage range (5) 0 (v ssa or v ref- tied to ground) -v ref+ v r ain (4) external input impedance see equation 1 for details --50 ? r adc (4)(6) sampling switch resistance - - 6 ? c adc (4) internal sample and hold capacitor -4-pf t lat (4) injection trigger conversion latency f adc = 30 mhz - - 0.100 s --3 (7) 1/f adc t latr (4) regular trigger conversion latency f adc = 30 mhz - - 0.067 s --2 (7) 1/f adc t s (4) sampling time f adc = 30 mhz 0.100 - 16 s 3-4801/f adc t stab (4) power-up time - 2 3 s
docid022063 rev 4 131/186 stm32f415xx, stm32f417xx electrical characteristics equation 1: r ain max formula the formula above ( equation 1 ) is used to dete rmine the maximum external impedance allowed for an error below 1/4 of lsb. n = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the adc_smpr1 register. t conv (4) total conversion time (including sampling time) f adc = 30 mhz 12-bit resolution 0.50 - 16.40 s f adc = 30 mhz 10-bit resolution 0.43 - 16.34 s f adc = 30 mhz 8-bit resolution 0.37 - 16.27 s f adc = 30 mhz 6-bit resolution 0.30 - 16.20 s 9 to 492 (t s for sampling +n-bit re solution for successive approximation) 1/f adc f s (4) sampling rate (f adc = 30 mhz, and t s = 3 adc cycles) 12-bit resolution single adc - - 2 msps 12-bit resolution interleave dual adc mode - - 3.75 msps 12-bit resolution interleave triple adc mode - - 6 msps i vref+ (4) adc v ref dc current consumption in conversion mode -300500a i vdda (4) adc v dda dc current consumption in conversion mode -1.61.8ma 1. v dd /v dda minimum value of 1.7 v is obtained when the device operat es in reduced temperature range, and with the use of an external power supply supervisor (refer to section : internal reset off ). 2. it is recommended to maintain the voltage difference between v ref+ and v dda below 1.8 v. 3. v dda -v ref+ < 1.2 v. 4. based on characterization, not tested in production. 5. v ref+ is internally connected to v dda and v ref- is internally connected to v ssa . 6. r adc maximum value is given for v dd =1.8 v, and minimum value for v dd =3.3 v. 7. for external triggers, a delay of 1/f pclk2 must be added to the latency specified in table 67 . table 67. adc characteristics (continued) symbol parameter conditions min typ max unit r ain k0.5 ? () f adc c adc 2 n 2 + () ln -------------------------------------------------------------- r adc ? =
electrical characteristics stm32f415xx, stm32f417xx 132/186 docid022063 rev 4 a note: adc accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this signifi cantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in section 5.3.16 does not affect the adc accuracy. figure 50. adc accuracy characteristics 1. see also table 68 . 2. example of an actual transfer curve. 3. ideal transfer curve. 4. end point correlation line. 5. e t = total unadjusted error: maximum deviation be tween the actual and the ideal transfer curves. eo = offset error: deviation between the fi rst actual transition and the first ideal one. table 68. adc accuracy at f adc = 30 mhz (1) 1. better performance could be achieved in restricted v dd , frequency and temperature ranges. symbol parameter test conditions typ max (2) 2. based on characterization, not tested in production. unit et total unadjusted error f pclk2 = 60 mhz, f adc = 30 mhz, r ain < 10 k , v dda = 1.8 (3) to 3.6 v 3. v dd /v dda minimum value of 1.7 v is obtained when the device operates in reduced temperature range, and with the use of an external po wer supply supervisor (refer to section : internal reset off ). 2 5 lsb eo offset error 1.5 2.5 eg gain error 1.5 3 ed differential linearity error 1 2 el integral linearity error 1.5 3 ai14395c e o e g 1l sb ideal 4095 4094 4093 5 4 3 2 1 0 7 6 1 2 3 456 7 4093 4094 4095 4096 (1) (2) e t e d e l (3) v dda v ssa v ref+ 4096 (or depending on package)] v dda 4096 [1lsb ideal =
docid022063 rev 4 133/186 stm32f415xx, stm32f417xx electrical characteristics eg = gain error: deviation between the last ideal transition and the last actual one. ed = differential linearity error: maximum deviation between actual steps and the ideal one. el = integral linearity error: maximum deviati on between any actual transition and the end point correlation line. figure 51. typical connecti on diagram using the adc 1. refer to table 67 for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 5 pf). a high c parasitic value downgrades conversion accuracy. to remedy this, f adc should be reduced. a i175 3 4 s tm 3 2f v dd ainx i l 1 a 0.6 v v t r ain (1) c p a r as itic v ain 0.6 v v t r adc (1) c adc (1) 12-bit converter sa mple a nd hold adc converter
electrical characteristics stm32f415xx, stm32f417xx 134/186 docid022063 rev 4 general pcb design guidelines power supply decoupling should be performed as shown in figure 52 or figure 53 , depending on whether v ref+ is connected to v dda or not. the 10 nf capacitors should be ceramic (good quality). they should be placed them as close as possible to the chip. figure 52. power supply and reference decoupling (v ref+ not connected to v dda ) 1. v ref+ and v ref? inputs are both available on ufbga176. v ref+ is also available on lqfp100, lqfp144, and lqfp176. when v ref+ and v ref? are not available, they ar e internally connected to v dda and v ssa . figure 53. power supply and reference decoupling (v ref+ connected to v dda ) 1. v ref+ and v ref? inputs are both available on ufbga176. v ref+ is also available on lqfp100, lqfp144, and lqfp176. when v ref+ and v ref? are not available, they ar e internally connected to v dda and v ssa . v ref+ s tm 3 2f v dda v ss a /v ref- 1 f // 10 nf 1 f // 10 nf a i175 3 5 ( s ee note 1) ( s ee note 1) v ref+ /v dda s tm 3 2f 1 f // 10 nf v ref? /v ss a a i175 3 6 ( s ee note 1) ( s ee note 1)
docid022063 rev 4 135/186 stm32f415xx, stm32f417xx electrical characteristics 5.3.21 temperature sensor characteristics 5.3.22 v bat monitoring characteristics table 69. temperature sensor characteristics symbol parameter min typ max unit t l (1) v sense linearity with temperature - 1 2c avg_slope (1) average slope - 2.5 mv/c v 25 (1) voltage at 25 c - 0.76 v t start (2) startup time - 6 10 s t s_temp (3)(2) adc sampling time when reading the temperature (1 c accuracy) 10 - - s 1. based on characterization, not tested in production. 2. guaranteed by design, not tested in production. 3. shortest sampling time can be determined in the application by multiple iterations. table 70. temperature sensor calibration values symbol parameter memory address ts_cal1 ts adc raw data acquired at temperature of 30 c, v dda =3.3 v 0x1fff 7a2c - 0x1fff 7a2d ts_cal2 ts adc raw data acquired at temperatur e of 110 c, v dda =3.3 v 0x1fff 7a2e - 0x1fff 7a2f table 71. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -50-k q ratio on v bat measurement - 2 - er (1) error on q ?1 - +1 % t s_vbat (2)(2) adc sampling time when reading the v bat 1 mv accuracy 5- -s 1. guaranteed by design, not tested in production. 2. shortest sampling time can be determined in the application by multiple iterations.
electrical characteristics stm32f415xx, stm32f417xx 136/186 docid022063 rev 4 5.3.23 embedded reference voltage the parameters given in table 72 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 14 . 5.3.24 dac electri cal characteristics table 72. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.18 1.21 1.24 v t s_vrefint (1) adc sampling time when reading the internal reference voltage 10 - - s v rerint_s (2) internal reference voltage spread over the temperature range v dd = 3 v - 3 5 mv t coeff (2) temperature coefficient - 30 50 ppm/c t start (2) startup time - 6 10 s 1. shortest sampling time can be determined in the application by multiple iterations. 2. guaranteed by design, not tested in production. table 73. internal reference voltage calibration values symbol parameter memory address v refin_cal raw data acquired at temperature of 30 c, v dda =3.3 v 0x1fff 7a2a - 0x1fff 7a2b table 74. dac characteristics symbol parameter min typ max unit comments v dda analog supply voltage 1.8 (1) -3.6 v v ref+ reference supply voltage 1.8 (1) -3.6vv ref+ v dda v ssa ground 0 - 0 v r load (2) resistive load with buffer on 5- - k r o (2) impedance output with buffer off -- 15 k when the buffer is off, the minimum resistive load between dac_out and v ss to have a 1% accuracy is 1.5 m c load (2) capacitive load - - 50 pf maximum capacitive load at dac_out pin (when the buffer is on). dac_out min (2) lower dac_out voltage with buffer on 0.2 - - v it gives the maximum output excursion of the dac. it corresponds to 12-bit input code (0x0e0) to (0xf1c) at v ref+ = 3.6 v and (0x1c7) to (0xe38) at v ref+ = 1.8 v dac_out max (2) higher dac_out voltage with buffer on --v dda ? 0.2 v
docid022063 rev 4 137/186 stm32f415xx, stm32f417xx electrical characteristics dac_out min (2) lower dac_out voltage with buffer off -0.5 - mv it gives the maximum output excursion of the dac. dac_out max (2) higher dac_out voltage with buffer off --v ref+ ? 1lsb v i vref+ (4) dac dc v ref current consumption in quiescent mode (standby mode) - 170 240 a with no load, worst code (0x800) at v ref+ = 3.6 v in terms of dc consumption on the inputs -50 75 with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs i dda (4) dac dc vdda current consumption in quiescent mode (3) - 280 380 a with no load, middle code (0x800) on the inputs - 475 625 a with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs dnl (4) differential non linearity difference between two consecutive code-1lsb) -- 0.5 lsb given for the dac in 10-bit configuration. -- 2 lsb given for the dac in 12-bit configuration. inl (4) integral non linearity (difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 1023) -- 1 lsb given for the dac in 10-bit configuration. -- 4 lsb given for the dac in 12-bit configuration. offset (4) offset error (difference between measured value at code (0x800) and the ideal value = v ref+ /2) -- 10 mv given for the dac in 12-bit configuration -- 3 lsb given for the dac in 10-bit at v ref+ = 3.6 v -- 12 lsb given for the dac in 12-bit at v ref+ = 3.6 v gain error (4) gain error - - 0.5 % given for the dac in 12-bit configuration t settling (4) settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when dac_out reaches final value 4lsb -3 6 s c load 50 pf, r load 5 k thd (4) total harmonic distortion buffer on -- - db c load 50 pf, r load 5 k table 74. dac characteristics (continued) symbol parameter min typ max unit comments
electrical characteristics stm32f415xx, stm32f417xx 138/186 docid022063 rev 4 figure 54. 12-bit buffered /non-buffered dac 1. the dac integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external oper ational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. 5.3.25 fsmc characteristics unless otherwise specified, the parameters given in table 75 to table 86 for the fsmc interface are derived from tests performed under the ambient temperature, f hclk frequency and v dd supply voltage cond itions summarized in table 14 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5v dd refer to section section 5.3.16: i/o po rt characteristics for more details on the input/output characteristics. update rate (2) max frequency for a correct dac_out change when small variation in the input code (from code i to i+1lsb) -- 1 ms/s c load 50 pf, r load 5 k t wakeup (4) wakeup time from off state (setting the enx bit in the dac control register) - 6.5 10 s c load 50 pf, r load 5 k input code between lowest and highest possible ones. psrr+ (2) power supply rejection ratio (to v dda ) (static dc measurement) - ?67 ?40 db no r load , c load = 50 pf 1. v dd /v dda minimum value of 1.7 v is obtained when the device operat es in reduced temperature range, and with the use of an external power supply supervisor (refer to section : internal reset off ). 2. guaranteed by design, not tested in production. 3. the quiescent mode corresponds to a state where the dac ma intains a stable output level to ensure that no dynamic consumption occurs. 4. guaranteed by characterization, not tested in production. table 74. dac characteristics (continued) symbol parameter min typ max unit comments r load c load b u ffered/non-b u ffered dac dacx_out b u ffer(1) 12-bit digit a l to a n a log converter a i17157
docid022063 rev 4 139/186 stm32f415xx, stm32f417xx electrical characteristics asynchronous waveforms and timings figure 55 through figure 58 represent asynchronous waveforms and table 75 through table 78 provide the corresponding ti mings. the results shown in these tables are obtained with the following fsmc configuration: ? addresssetuptime = 1 ? addressholdtime = 0x1 ? datasetuptime = 0x1 ? busturnaroundduration = 0x0 in all timing tables, the t hclk is the hclk clock period. figure 55. asynchronous non-multiplexed sram/psram/nor read waveforms 1. mode 2/b, c and d only. in mode 1, fsmc_nadv is not used. table 75. asynchronous non-multiple xed sram/psram/nor read timings (1)(2) symbol parameter min max unit t w(ne) fsmc_ne low time 2t hclk ?0.5 2 t hclk +1 ns t v(noe_ne) fsmc_nex low to fsmc_noe low 0.5 3 ns t w(noe) fsmc_noe low time 2t hclk ?2 2t hclk + 2 ns t h(ne_noe) fsmc_noe high to fsmc_ne high hold time 0 - ns t v(a_ne) fsmc_nex low to fsmc_a valid - 4.5 ns t h(a_noe) address hold time after fsmc_noe high 4 - ns data fsmc_ne fsmc_nbl[1:0] fsmc_d[15:0] t v(bl_ne) t h(data_ne) fsmc_noe address fsmc_a[25:0] t v(a_ne) fsmc_nwe t su(data_ne) t w(ne) ai14991c w(noe) t t v(noe_ne) t h(ne_noe) t h(data_noe) t h(a_noe) t h(bl_noe) t su(data_noe) fsmc_nadv (1) t v(nadv_ne) t w(nadv)
electrical characteristics stm32f415xx, stm32f417xx 140/186 docid022063 rev 4 figure 56. asynchronous non-multiplexed sram/psram/nor write waveforms 1. mode 2/b, c and d only. in mode 1, fsmc_nadv is not used. t v(bl_ne) fsmc_nex low to fsmc_bl valid - 1.5 ns t h(bl_noe) fsmc_bl hold time after fsmc_noe high 0 - ns t su(data_ne) data to fsmc_nex high setup time t hclk +4 - ns t su(data_noe) data to fsmc_noex high setup time t hclk +4 - ns t h(data_noe) data hold time after fsmc_noe high 0 - ns t h(data_ne) data hold time after fsmc_nex high 0 - ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low - 2 ns t w(nadv) fsmc_nadv low time - t hclk ns 1. c l = 30 pf. 2. based on characterization, not tested in production. table 76. asynchronous non-multiple xed sram/psram/nor write timings (1)(2) symbol parameter min max unit t w(ne) fsmc_ne low time 3t hclk 3t hclk + 4 ns t v(nwe_ne) fsmc_nex low to fsmc_nwe low t hclk ?0.5 t hclk +0.5 ns t w(nwe) fsmc_nwe low time t hclk ?1 t hclk +2 ns t h(ne_nwe) fsmc_nwe high to fsmc_ne high hold time t hclk ?1 - ns t v(a_ne) fsmc_nex low to fsmc_a valid - 0 ns table 75. asynchronous non-multiple xed sram/psram/nor read timings (1)(2) nbl data fsmc_nex fsmc_nbl[1:0] fsmc_d[15:0] t v(bl_ne) t h(data_nwe) fsmc_noe address fsmc_a[25:0] t v(a_ne) t w(nwe) fsmc_nwe t v(nwe_ne) t h(ne_nwe) t h(a_nwe) t h(bl_nwe) t v(data_ne) t w(ne) ai14990 fsmc_nadv (1) t v(nadv_ne) t w(nadv)
docid022063 rev 4 141/186 stm32f415xx, stm32f417xx electrical characteristics figure 57. asynchronous multiplexed psram/nor read waveforms t h(a_nwe) address hold time after fsmc_nwe high t hclk ? 2 - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 1.5 ns t h(bl_nwe) fsmc_bl hold time after fsmc_nwe high t hclk ? 1 - ns t v(data_ne) data to fsmc_nex low to data valid - t hclk +3 ns t h(data_nwe) data hold time after fsmc_nwe high t hclk ?1 - ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low - 2 ns t w(nadv) fsmc_nadv low time - t hclk +0.5 ns 1. c l = 30 pf. 2. based on characterization, not tested in production. table 77. asynchronous multiplexed psram/nor read timings (1)(2) symbol parameter min max unit t w(ne) fsmc_ne low time 3t hclk ?1 3t hclk +1 ns t v(noe_ne) fsmc_nex low to fsmc_noe low 2t hclk ?0.5 2t hclk +0.5 ns t w(noe) fsmc_noe low time t hclk ?1 t hclk +1 ns t h(ne_noe) fsmc_noe high to fsmc_ne high hold time 0 - ns t v(a_ne) fsmc_nex low to fsmc_a valid - 3 ns table 76. asynchronous non-multiple xed sram/psram/nor write timings (1)(2) nbl data fsmc_nbl[1:0] fsmc_ ad[15:0] t v(bl_ne) t h(data_ne) address fsmc_a[25:16] t v(a_ne) fsmc_nwe t v(a_ne) ai14 8 92 b address fsmc_nadv t v(nadv_ne) t w(nadv) t su(data_ne) t h(ad_nadv) fsmc_ne fsmc_noe t w(ne) t w(noe) t v(noe_ne) t h(ne_noe) t h(a_noe) t h(bl_noe) t su(data_noe) t h(data_noe)
electrical characteristics stm32f415xx, stm32f417xx 142/186 docid022063 rev 4 figure 58. asynchronous multip lexed psram/nor write waveforms t v(nadv_ne) fsmc_nex low to fsmc_nadv low 1 2 ns t w(nadv) fsmc_nadv low time t hclk ? 2 t hclk +1 ns t h(ad_nadv) fsmc_ad(adress) valid hold time after fsmc_nadv high) t hclk -ns t h(a_noe) address hold time after fsmc_noe high t hclk ?1 - ns t h(bl_noe) fsmc_bl time after fsmc_noe high 0 - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 2 ns t su(data_ne) data to fsmc_nex high setup time t hclk +4 - ns t su(data_noe) data to fsmc_noe high setup time t hclk +4 - ns t h(data_ne) data hold time after fsmc_nex high 0 - ns t h(data_noe) data hold time after fsmc_noe high 0 - ns 1. c l = 30 pf. 2. based on characterization, not tested in production. table 78. asynchrono us multiplexed psram /nor write timings (1)(2) symbol parameter min max unit t w(ne) fsmc_ne low time 4t hclk ?0.5 4t hclk +3 ns t v(nwe_ne) fsmc_nex low to fsmc_nwe low t hclk ?0.5 t hclk -0.5 ns t w(nwe) fsmc_nwe low tim e 2t hclk ?0.5 2t hclk +3 ns table 77. asynchronous multip lexed psram/nor read timings (1)(2) (continued) nbl data fsmc_nex fsmc_nbl[1:0] fsmc_ ad[15:0] t v(bl_ne) t h(data_nwe) fsmc_noe address fsmc_a[25:16] t v(a_ne) t w(nwe) fsmc_nwe t v(nwe_ne) t h(ne_nwe) t h(a_nwe) t h(bl_nwe) t v(a_ne) t w(ne) ai14 8 91b address fsmc_nadv t v(nadv_ne) t w(nadv) t v(data_nadv) t h(ad_nadv)
docid022063 rev 4 143/186 stm32f415xx, stm32f417xx electrical characteristics synchronous waveforms and timings figure 59 through figure 62 represent synchronous waveforms and table 80 through table 82 provide the corresponding ti mings. the results shown in these tables are obtained with the following fsmc configuration: ? burstaccessmode = fsmc_burstaccessmode_enable; ? memorytype = fsmc_memorytype_cram; ? writeburst = fsmc_writeburst_enable; ? clkdivision = 1; (0 is not supported, see the stm32f40xxx/41xxx reference manual) ? datalatency = 1 for nor flash; datalatency = 0 for psram in all timing tables, the t hclk is the hclk clock period (with maximum fsmc_clk = 60 mhz). t h(ne_nwe) fsmc_nwe high to fsmc_ne high hold time t hclk -ns t v(a_ne) fsmc_nex low to fsmc_a valid - 0 ns t v(nadv_ne) fsmc_nex low to fsmc_nadv low 1 2 ns t w(nadv) fsmc_nadv low time t hclk ? 2 t hclk + 1 ns t h(ad_nadv) fsmc_ad(address) valid hold time after fsmc_nadv high) t hclk ?2 - ns t h(a_nwe) address hold time after fsmc_nwe high t hclk -ns t h(bl_nwe) fsmc_bl hold time after fsmc_nwe high t hclk ?2 - ns t v(bl_ne) fsmc_nex low to fsmc_bl valid - 1.5 ns t v(data_nadv) fsmc_nadv high to data valid - t hclk ?0.5 ns t h(data_nwe) data hold time after fsmc_nwe high t hclk -ns 1. c l = 30 pf. 2. based on characterization, not tested in production. table 78. asynchrono us multiplexed psram /nor write timings (1)(2)
electrical characteristics stm32f415xx, stm32f417xx 144/186 docid022063 rev 4 figure 59. synchronous multiplexed nor/psram read timings table 79. synchronous multiplexed nor/psram read timings (1)(2) symbol parameter min max unit t w(clk) fsmc_clk period 2t hclk -ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x=0..2) - 0 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x= 0?2) 2 - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - 2 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 2 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x=16?25) - 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x=16?25) 0 - ns t d(clkl-noel) fsmc_clk low to fsmc_noe low - 0 ns t d(clkl-noeh) fsmc_clk low to fsmc_noe high 2 - ns t d(clkl-adv) fsmc_clk low to fsmc_ad[15:0] valid - 4.5 ns t d(clkl-adiv) fsmc_clk low to fsmc_ad[15:0] invalid 0 - ns t su(adv-clkh) fsmc_a/d[15:0] valid data before fsmc_clk high 6 - ns fsmc_clk fsmc_nex fsmc_nadv fsmc_a[25:16] fsmc_noe fsmc_ad[15:0] ad[15:0] d1 d2 fsmc_nwait (waitcfg = 1b, waitpol + 0b) fsmc_nwait (waitcfg = 0b, waitpol + 0b) t w(clk) t w(clk) data latency = 0 busturn = 0 t d(clkl-nexl) t d(clkl-nexh) t d(clkl-nadvl) t d(clkl-av) t d(clkl-nadvh) t d(clkl-aiv) t d(clkl-noel) t d(clkl-noeh) t d(clkl-adv) t d(clkl-adiv) t su(adv-clkh) t h(clkh-adv) t su(adv-clkh) t h(clkh-adv) t su(nwaitv-clkh) t h(clkh-nwaitv) t su(nwaitv-clkh) t h(clkh-nwaitv) t su(nwaitv-clkh) t h(clkh-nwaitv) ai14893g
docid022063 rev 4 145/186 stm32f415xx, stm32f417xx electrical characteristics figure 60. synchronous multiplexed psram write timings t h(clkh-adv) fsmc_a/d[15:0] valid data after fsmc_clk high 0 - ns t su(nwait-clkh) fsmc_nwait valid before fsmc_clk high 4 - ns t h(clkh-nwait) fsmc_nwait valid after fsmc_clk high 0 - ns 1. c l = 30 pf. 2. based on characterization, not tested in production. table 80. synchronous multiplexed psram write timings (1)(2) symbol parameter min max unit t w(clk) fsmc_clk period 2t hclk -ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x=0..2) - 1 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x= 0?2) 1 - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - 0 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 0 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x=16?25) - 0 ns table 79. synchronous multiple xed nor/psram read timings (1)(2) (continued) fsmc_clk fsmc_nex fsmc_nadv fsmc_a[25:16] fsmc_nwe fsmc_ad[15:0] ad[15:0] d1 d2 fsmc_nwait (waitcfg = 0b, waitpol + 0b) t w(clk) t w(clk) data latency = 0 busturn = 0 t d(clkl-nexl) t d(clkl-nexh) t d(clkl-nadvl) t d(clkl-av) t d(clkl-nadvh) t d(clkl-aiv) t d(clkl-nweh) t d(clkl-nwel) t d(clkl-nblh) t d(clkl-adv) t d(clkl-adiv) t d(clkl-data) t su(nwaitv-clkh) t h(clkh-nwaitv) ai14992g t d(clkl-data) fsmc_nbl
electrical characteristics stm32f415xx, stm32f417xx 146/186 docid022063 rev 4 figure 61. synchronous non-multiplexed nor/psram read timings t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x=16?25) 8 - ns t d(clkl-nwel) fsmc_clk low to fsmc_nwe low - 0.5 ns t d(clkl-nweh) fsmc_clk low to fsmc_nwe high 0 - ns t d(clkl-adiv) fsmc_clk low to fsmc_ad[15:0] invalid 0 - ns t d(clkl-data) fsmc_a/d[15:0] valid data after fsmc_clk low - 3 ns t d(clkl-nblh) fsmc_clk low to fsmc_nbl high 0 - ns t su(nwait-clkh) fsmc_nwait valid before fsmc_clk high 4 - ns t h(clkh-nwait) fsmc_nwait valid after fsmc_clk high 0 - ns 1. c l = 30 pf. 2. based on characterization, not tested in production. table 81. synchronous non-multiplexed nor/psram read timings (1)(2) symbol parameter min max unit t w(clk) fsmc_clk period 2t hclk ?0.5 - ns t d(clkl-nexl) fsmc_clk low to fsmc_nex low (x=0..2) - 0.5 ns table 80. synchronous multiplexed psram write timings (1)(2) fsmc_clk fsmc_nex fsmc_a[25:0] fsmc_noe fsmc_d[15:0] d1 d2 fsmc_nwait (waitcfg = 1b, waitpol + 0b) fsmc_nwait (waitcfg = 0b, waitpol + 0b) t w(clk) t w(clk) data latency = 0 busturn = 0 t d(clkl-nexl) t d(clkl-nexh) t d(clkl-av) t d(clkl-aiv) t d(clkl-noel) t d(clkl-noeh) t su(dv-clkh) t h(clkh-dv) t su(dv-clkh) t h(clkh-dv) t su(nwaitv-clkh) t h(clkh-nwaitv) t su(nwaitv-clkh) t h(clkh-nwaitv) t su(nwaitv-clkh) t h(clkh-nwaitv) ai14894f fsmc_nadv t d(clkl-nadvl) t d(clkl-nadvh)
docid022063 rev 4 147/186 stm32f415xx, stm32f417xx electrical characteristics figure 62. synchronous non-multi plexed psram write timings t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x= 0?2) 0 - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - 2 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 3 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x=16?25) - 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x=16?25) 2 - ns t d(clkl-noel) fsmc_clk low to fsmc_noe low - 0.5 ns t d(clkl-noeh) fsmc_clk low to fsmc_noe high 1.5 - ns t su(dv-clkh) fsmc_d[15:0] valid data before fsmc_clk high 6 - ns t h(clkh-dv) fsmc_d[15:0] valid data after fsmc_clk high 3 - ns t su(nwait-clkh) fsmc_nwait valid before fsmc_clk high 4 - ns t h(clkh-nwait) fsmc_nwait valid after fsmc_clk high 0 - ns 1. c l = 30 pf. 2. based on characterization, not tested in production. table 81. synchronous non-mult iplexed nor/psram read timings (1)(2) (continued) fsmc_clk fsmc_nex fsmc_a[25:0] fsmc_nwe fsmc_d[15:0] d1 d2 fsmc_nwait (waitcfg = 0b, waitpol + 0b) t w(clk) t w(clk) data latency = 0 busturn = 0 t d(clkl-nexl) t d(clkl-nexh) t d(clkl-av) t d(clkl-aiv) t d(clkl-nweh) t d(clkl-nwel) t d(clkl-data) t su(nwaitv-clkh) t h(clkh-nwaitv) ai14993g fsmc_nadv t d(clkl-nadvl) t d(clkl-nadvh) t d(clkl-data) fsmc_nbl t d(clkl-nblh)
electrical characteristics stm32f415xx, stm32f417xx 148/186 docid022063 rev 4 pc card/compactflash controller waveforms and timings figure 63 through figure 68 represent synchronous waveforms, and table 83 and table 84 provide the corresponding timings. the results shown in this table are obtained with the following fsmc configuration: ? com.fsmc_setuptime = 0x04; ? com.fsmc_waitsetuptime = 0x07; ? com.fsmc_holdsetuptime = 0x04; ? com.fsmc_hizsetuptime = 0x00; ? att.fsmc_setuptime = 0x04; ? att.fsmc_waitsetuptime = 0x07; ? att.fsmc_holdsetuptime = 0x04; ? att.fsmc_hizsetuptime = 0x00; ? io.fsmc_setuptime = 0x04; ? io.fsmc_waitsetuptime = 0x07; ? io.fsmc_holdsetuptime = 0x04; ? io.fsmc_hizsetu ptime = 0x00; ? tclrsetuptime = 0; ? tarsetuptime = 0. in all timing tables, the t hclk is the hclk clock period. table 82. synchronous non-multi plexed psram write timings (1)(2) 1. c l = 30 pf. 2. based on characterization, not tested in production. symbol parameter min max unit t w(clk) fsmc_clk period 2t hclk -ns t d(clkl-nexl) fsmc_clk low to fsmc_n ex low (x=0..2) - 1 ns t d(clkl-nexh) fsmc_clk low to fsmc_nex high (x= 0?2) 1 - ns t d(clkl-nadvl) fsmc_clk low to fsmc_nadv low - 7 ns t d(clkl-nadvh) fsmc_clk low to fsmc_nadv high 6 - ns t d(clkl-av) fsmc_clk low to fsmc_ax valid (x=16?25) - 0 ns t d(clkl-aiv) fsmc_clk low to fsmc_ax invalid (x=16?25) 6 - ns t d(clkl-nwel) fsmc_clk low to fsmc_nwe low - 1 ns t d(clkl-nweh) fsmc_clk low to fsmc_nwe high 2 - ns t d(clkl-data) fsmc_d[15:0] valid data after fsmc_clk low - 3 ns t d(clkl-nblh) fsmc_clk low to fsmc_nbl high 3 - ns t su(nwait-clkh) fsmc_nwait valid before fsmc_clk high 4 - ns t h(clkh-nwait) fsmc_nwait valid after fsmc_clk high 0 - ns
docid022063 rev 4 149/186 stm32f415xx, stm32f417xx electrical characteristics figure 63. pc card/compactflash controll er waveforms for common memory read access 1. fsmc_nce4_2 remains high (inac tive during 8-bit access. figure 64. pc card/compactflash contro ller waveforms for co mmon memory write access fsmc_nwe t w(noe) fsmc_n oe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_2 (1) fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(nce4_1-noe) t su(d-noe) t h(noe-d) t v(ncex-a) t d(nreg-ncex) t d(niord-ncex) t h(ncex-ai) t h(ncex-nreg) t h(ncex-niord) t h(ncex- niowr ) ai14 8 95 b t d(nce4_1-nwe) t w(nwe) t h(nwe-d) t v(nce4_1-a) t d(nreg-nce4_1) t d(niord-nce4_1) t h(nce4_1-ai) memxhiz =1 t v(nwe-d) t h(nce4_1-nreg) t h(nce4_1-niord) t h(nce4_1-niowr) ai14 8 96 b fsmc_nwe fsmc_n oe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(nwe-nce4_1) t d(d-nwe) fsmc_nce4_2 high
electrical characteristics stm32f415xx, stm32f417xx 150/186 docid022063 rev 4 figure 65. pc card/compactflash controller waveforms for attribute memory read access 1. only data bits 0...7 are read (bits 8...15 are disregarded). t d(nce4_1-noe) t w(noe) t su(d-noe) t h(noe-d) t v(nce4_1-a) t h(nce4_1-ai) t d(nreg-nce4_1) t h(nce4_1-nreg) ai14 8 97 b fsmc_nwe fsmc_noe fsmc_d[15:0] (1) fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(noe-nce4_1) high
docid022063 rev 4 151/186 stm32f415xx, stm32f417xx electrical characteristics figure 66. pc card/compactflash controller waveforms for attribute memory write access 1. only data bits 0...7 are driven (bits 8...15 remains hi-z). figure 67. pc card/compactflash controll er waveforms for i/o space read access t w(nwe) t v(nce4_1-a) t d(nreg-nce4_1) t h(nce4_1-ai) t h(nce4_1-nreg) t v(nwe-d) ai14 8 9 8b fsmc_nwe fsmc_noe fsmc_d[7:0](1) fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(nwe-nce4_1) high t d(nce4_1-nwe) t d(niord-nce4_1) t w(niord) t su(d-niord) t d(niord-d) t v(ncex-a) t h(nce4_1-ai) ai14 8 99b fsmc_nwe fsmc_noe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord
electrical characteristics stm32f415xx, stm32f417xx 152/186 docid022063 rev 4 figure 68. pc card/compactflash controller waveforms for i/o space write access t d(nce4_1-niowr) t w(niowr) t v(ncex-a) t h(nce4_1-ai) t h(niowr-d) attxhiz =1 t v(niowr-d) ai14900c fsmc_nwe fsmc_noe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord table 83. switching characteristics fo r pc card/cf read and write cycles in attribute/common space (1)(2) symbol parameter min max unit t v(ncex-a) fsmc_ncex low to fsmc_ay valid - 0 ns t h(ncex_ai) fsmc_ncex high to fsmc_ax invalid 4 - ns t d(nreg-ncex) fsmc_ncex low to fsmc_nreg valid - 3.5 ns t h(ncex-nreg) fsmc_ncex high to fsmc_nreg invalid t hclk +4 - ns t d(ncex-nwe) fsmc_ncex low to fsmc_nwe low - 5t hclk +0.5 ns t d(ncex-noe) fsmc_ncex low to fsmc_noe low - 5t hclk +0.5 ns t w(noe) fsmc_noe low width 8t hclk ?1 8t hclk +1 ns t d(noe_ncex) fsmc_noe high to fsmc_ncex high 5t hclk +2.5 - ns t su (d-noe) fsmc_d[15:0] valid data before fsmc_noe high 4.5 - ns t h(n0e-d) fsmc_n0e high to fsmc_d[15:0] invalid 3 - ns t w(nwe) fsmc_nwe low width 8t hclk ?0.5 8t hclk + 3 ns t d(nwe_ncex) fsmc_nwe high to fsmc_ncex high 5t hclk ?1 -ns t d(ncex-nwe) fsmc_ncex low to fsmc_nwe low - 5t hclk + 1 ns t v(nwe-d) fsmc_nwe low to fsmc_d[15:0] valid - 0 ns t h (nwe-d) fsmc_nwe high to fsmc_d[15:0] invalid 8t hclk ?1 - ns t d (d-nwe) fsmc_d[15:0] valid before fsmc_nwe high 13t hclk ?1 - ns 1. c l = 30 pf. 2. based on characterization, not tested in production.
docid022063 rev 4 153/186 stm32f415xx, stm32f417xx electrical characteristics nand controller waveforms and timings figure 69 through figure 72 represent synchronous waveforms, and table 85 and table 86 provide the corresponding timings. the results shown in this table are obtained with the following fsmc configuration: ? com.fsmc_setuptime = 0x01; ? com.fsmc_waitsetuptime = 0x03; ? com.fsmc_holdsetuptime = 0x02; ? com.fsmc_hizsetuptime = 0x01; ? att.fsmc_setuptime = 0x01; ? att.fsmc_waitsetuptime = 0x03; ? att.fsmc_holdsetuptime = 0x02; ? att.fsmc_hizsetuptime = 0x01; ? bank = fsmc_bank_nand; ? memorydatawidth = fsmc_memorydatawidth_16b; ? ecc = fsmc_ecc_enable; ? eccpagesize = fsmc_eccpagesize_512bytes; ? tclrsetuptime = 0; ? tarsetuptime = 0. in all timing tables, the t hclk is the hclk clock period. table 84. switching characteristics fo r pc card/cf read and write cycles in i/o space (1)(2) symbol parameter min max unit t w(niowr) fsmc_niowr low width 8t hclk ?1 - ns t v(niowr-d) fsmc_niowr low to fsmc_d[15:0] valid - 5t hclk ? 1 ns t h(niowr-d) fsmc_niowr high to fsmc_d[15:0] invalid 8t hclk ? 2 - ns t d(nce4_1-niowr) fsmc_nce4_1 low to fsmc_niowr valid - 5t hclk + 2.5 ns t h(ncex-niowr) fsmc_ncex high to fsmc_niowr invalid 5t hclk ?1.5 - ns t d(niord-ncex) fsmc_ncex low to fsmc_niord valid - 5t hclk + 2 ns t h(ncex-niord) fsmc_ncex high to fsmc_niord) valid 5t hclk ? 1.5 - ns t w(niord) fsmc_niord low width 8t hclk ?0.5 - ns t su(d-niord) fsmc_d[15:0] valid before fsmc_niord high 9 - ns t d(niord-d) fsmc_d[15:0] valid after fsmc_niord high 0 - ns 1. c l = 30 pf. 2. based on characterization, not tested in production.
electrical characteristics stm32f415xx, stm32f417xx 154/186 docid022063 rev 4 figure 69. nand controller waveforms for read access figure 70. nand controller waveforms for write access fsmc_nwe fsmc_noe (nre) fsmc_d[15:0] t su(d-noe) t h(noe-d) ai14901c ale (fsmc_a17) cle (fsmc_a16) fsmc_ncex t d(ale-noe) t h(noe-ale) t h(nwe-d) t v(nwe-d) ai14902c fsmc_nwe fsmc_noe (nre) fsmc_d[15:0] ale (fsmc_a17) cle (fsmc_a16) fsmc_ncex t d(ale-nwe) t h(nwe-ale)
docid022063 rev 4 155/186 stm32f415xx, stm32f417xx electrical characteristics figure 71. nand controller waveforms for common memory read access figure 72. nand controller wavefo rms for common memory write access table 85. switching characteristics for nand flash read cycles (1) 1. c l = 30 pf. symbol parameter min max unit t w(n0e) fsmc_noe low width 4t hclk ? 0.5 4t hclk + 3 ns t su(d-noe) fsmc_d[15-0] valid data before fsmc_noe high 10 - ns t h(noe-d) fsmc_d[15-0] valid data after fsmc_noe high 0 - ns t d(ale-noe) fsmc_ale valid before fsmc_noe low - 3t hclk ns t h(noe-ale) fsmc_nwe high to fsmc_ale invalid 3t hclk ? 2 - ns fsmc_nwe fsmc_n oe fsmc_d[15:0] t w(noe) t su(d-noe) t h(noe-d) ai14912c ale (fsmc_a17) cle (fsmc_a16) fsmc_ncex t d(ale-noe) t h(noe-ale) t w(nwe) t h(nwe-d) t v(nwe-d) ai14913c fsmc_nwe fsmc_n oe fsmc_d[15:0] t d(d-nwe) ale (fsmc_a17) cle (fsmc_a16) fsmc_ncex t d(ale-noe) t h(noe-ale)
electrical characteristics stm32f415xx, stm32f417xx 156/186 docid022063 rev 4 5.3.26 camera interface (d cmi) timing specifications unless otherwise specified, the parameters given in table 87 for dcmi are derived from tests performed under the ambient temperature, f hclk frequency and v dd supply voltage summarized in table 13 , with the following configuration: ? pck polarity: falling ? vsync and hsync polarity: high ? data format: 14 bits figure 73. dcmi timing diagram table 86. switching characteris tics for nand flash write cycles (1) 1. c l = 30 pf. symbol parameter min max unit t w(nwe) fsmc_nwe low width 4t hclk ?1 4t hclk + 3 ns t v(nwe-d) fsmc_nwe low to fsmc_d[15-0] valid - 0 ns t h(nwe-d) fsmc_nwe high to fsmc_d[15-0] invalid 3t hclk ?2 - ns t d(d-nwe) fsmc_d[15-0] valid before fsmc_nwe high 5t hclk ?3 - ns t d(ale-nwe) fsmc_ale valid before fsmc_nwe low - 3t hclk ns t h(nwe-ale) fsmc_nwe high to fsmc_ale invalid 3t hclk ?2 - ns table 87. dcmi characteristics (1) symbol paramete rminmaxunit frequency ratio dcmi_pixclk/f hclk -0.4 dcmi_pixclk pixel clock input - 54 mhz d pixel pixel clock input duty cycle 30 70 % ms32414v1 pixel clock t su(vsync) t su(hsync) hsync vsync data[0:13] 1/dcmi_pixclk t h(hsync) t h(hsync) t su(data) t h(data)
docid022063 rev 4 157/186 stm32f415xx, stm32f417xx electrical characteristics 5.3.27 sd/sdio mmc card host in terface (sdio) characteristics unless otherwise specified, the parameters given in table 88 are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 14 with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5v dd refer to section 5.3.16: i/o port characteristics for more details on the input/output characteristics. figure 74. sdio high-speed mode t su(data) data input setup time 2.5 - ns t h(data) data hold time 1 - t su(hsync) , t su(vsync) hsync/vsync input setup time 2 - t h(hsync) , t h(vsync) hsync/vsync input hold time 0.5 - 1. data based on characterization results, not tested in production. table 87. dcmi characteristics (1) (continued) symbol paramete rminmaxunit t w(ckh) ck d, cmd (output) d, cmd (input) t c t w(ckl) t ov t oh t isu t ih t f t r ai14 88 7
electrical characteristics stm32f415xx, stm32f417xx 158/186 docid022063 rev 4 figure 75. sd default mode 5.3.28 rtc characteristics ck d, cmd (output) t ovd t ohd ai14 888 table 88. dynamic characteristic s: sd / mmc characteristics (1) symbol paramete r conditions min typ max unit f pp clock frequency in data transfer mode 0 48 mhz sdio_ck/f pclk2 frequency ratio - - 8/3 - t w(ckl) clock low time fpp = 48 mhz 8.5 9 - ns t w(ckh) clock high time fpp = 48 mhz 8.3 10 - cmd, d inputs (referenced to ck) in mmc and sd hs mode t isu input setup time hs fpp = 48 mhz 3 - - ns t ih input hold time hs fpp = 48 mhz 0 - - cmd, d outputs (referenced to ck) in mmc and sd hs mode t ov output valid time hs fpp = 48 mhz - 4.5 6 ns t oh output hold time hs fpp = 48 mhz 1 - - cmd, d inputs (referenced to ck) in sd default mode t isud input setup time sd fpp = 24 mhz 1.5 - - ns t ihd input hold time sd fpp = 24 mhz 0.5 - - cmd, d outputs (referenced to ck) in sd default mode t ovd output valid default time sd fpp = 24 mhz - 4.5 7 ns t ohd output hold default time sd fpp = 24 mhz 0.5 - - 1. data based on characterization re sults, not tested in production. table 89. rtc characteristics symbol parameter conditions min max -f pclk1 /rtcclk frequency ratio any read/write operation from/to an rtc register 4-
docid022063 rev 4 159/186 stm32f415xx, stm32f417xx package characteristics 6 package characteristics 6.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark.
package characteristics stm32f415xx, stm32f417xx 160/186 docid022063 rev 4 figure 76. wlcsp90 - 0.400 mm pitch wafe r level chip size package outline bump side side view detail a wafer back side a1 ball location a1 detail a rotated by 90 c eee d a0jw_me seating plane a2 a b e e e1 e g f e2 table 90. wlcsp90 - 0.400 mm pitch wafer level chip size package mechanical data symbol millimeters inches (1) min typ max min typ max a 0.520 0.570 0.620 0.0205 0.0224 0.0244 a1 0.165 0.190 0.215 0.0065 0.0075 0.0085 a2 0.350 0.380 0.410 0.0138 0.015 0.0161 b 0.240 0.270 0.300 0.0094 0.0106 0.0118 d 4.178 4.218 4.258 0.1645 0.1661 0.1676 e 3.964 3.969 4.004 0.1561 0.1563 0.1576 e 0.400 0.0157 e1 3.600 0.1417 e2 3.200 0.126 f 0.312 0.0123 g 0.385 0.0152 eee 0.050 0.0020 1. values in inches are converted from mm and rounded to 4 decimal digits.
docid022063 rev 4 161/186 stm32f415xx, stm32f417xx package characteristics figure 77. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline 1. drawing is not to scale. ai1439 8b a a2 a1 c l1 l e e1 d d1 e b table 91. lqfp64 ? 10 x 10 mm 64 pin low-prof ile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 12.000 0.4724 d1 10.000 0.3937 e 12.000 0.4724 e1 10.000 0.3937 e 0.500 0.0197 0 3.5 7 0 3.5 7 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 n number of pins 64 1. values in inches are converted from mm and rounded to 4 decimal digits.
package characteristics stm32f415xx, stm32f417xx 162/186 docid022063 rev 4 figure 78. lqfp64 recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. 4 8 32 49 64 17 116 1.2 0.3 33 10.3 12.7 10.3 0.5 7. 8 12.7 ai14909
docid022063 rev 4 163/186 stm32f415xx, stm32f417xx package characteristics figure 79. lqfp100, 14 x 14 mm 100-pin low-profile quad flat package outline 1. drawing is not to scale. e identification pin 1 gauge plane 0.25 mm seating plane d d1 d3 e3 e1 e k ccc c c 1 25 26 100 76 75 51 50 1l_me_v4 a2 a a1 l1 l c b a1 table 92. lqpf100 ? 14 x 14 mm 100-pin low-profile quad flat package mechanical data (1) symbol millimeters inches min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 12.000 0.4724 e 15.80v 16.000 16.200 0.6220 0.6299 0.6378 e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 12.000 0.4724 e 0.500 0.0197 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 03.57 03.57 ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
package characteristics stm32f415xx, stm32f417xx 164/186 docid022063 rev 4 figure 80. lqfp100 recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. 75 51 50 76 0.5 0.3 16.7 14.3 100 26 12.3 25 1.2 16.7 1 ai14906
docid022063 rev 4 165/186 stm32f415xx, stm32f417xx package characteristics figure 81. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package outline 1. drawing is not to scale. d1 d3 d e1 e3 e e pin 1 identification 73 72 37 36 109 144 10 8 1 aa2a1 b c a1 l l1 k seating plane c ccc c 0.25 mm gage plane me_1a table 93. lqfp144, 20 x 20 mm, 144-pin low-pr ofile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 21.800 22.000 22.2 00 0.8583 0.8661 0.874 d1 19.800 20.000 20.200 0.7795 0.7874 0.7953 d3 17.500 0.689 e 21.800 22.000 22.200 0.8583 0.8661 0.8740 e1 19.800 20.000 20.200 0.7795 0.7874 0.7953 e3 17.500 0.6890 e 0.500 0.0197 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394
package characteristics stm32f415xx, stm32f417xx 166/186 docid022063 rev 4 figure 82. lqfp144 recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. k 03.57 03.57 ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 93. lqfp144, 20 x 20 mm, 144-pin low-pr ofile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max ai14905c 0.5 0.35 19.9 17.85 22.6 1.35 22.6 19.9 1 36 37 72 73 108 109 144
docid022063 rev 4 167/186 stm32f415xx, stm32f417xx package characteristics figure 83. ufbga176+25 - ultra thin fine pi tch ball grid array 10 10 0.6 mm, package outline 1. drawing is not to scale. table 94. ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.460 0.530 0.600 0.0181 0.0209 0.0236 a1 0.050 0.080 0.110 0.002 0.0031 0.0043 a2 0.400 0.450 0.500 0.0157 0.0177 0.0197 b 0.230 0.280 0.330 0.0091 0.0110 0.0130 d 9.900 10.000 10.100 0.3898 0.3937 0.3976 e 9.900 10.000 10.100 0.3898 0.3937 0.3976 e 0.650 0.0256 f 0.425 0.450 0.475 0.0167 0.0177 0.0187 ddd 0.080 0.0031 eee 0.150 0.0059 fff 0.080 0.0031 a0e7_me_v4 seating plane a2 c ddd a1 a e f f e r a 15 1 bottom view e d top view ?b (176 + 25 balls) b a b eee ? m fff ? m c c a c a1 ball identifier a1 ball index area
package characteristics stm32f415xx, stm32f417xx 168/186 docid022063 rev 4 figure 84. lqfp176 24 x 24 mm, 176-pin low-profile quad flat package outline 1. drawing is not to scale. ccc c seating plane c aa2 a1 c 0.25 mm gauge plane hd d a1 l l1 k 89 88 e he 45 44 e 1 176 pin 1 identification b 133 132 1t_me zd ze table 95. lqfp176, 24 x 24 mm, 176-pin low-pr ofile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 a2 1.350 1.450 0.0531 0.0060 b 0.170 0.270 0.0067 0.0106 c 0.090 0.200 0.0035 0.0079 d 23.900 24.100 0.9409 0.9488 e 23.900 24.100 0.9409 0.9488 e 0.500 0.0197 hd 25.900 26.100 1.0200 1.0276 he 25.900 26.100 1.0200 1.0276 l 0.450 0.750 0.0177 0.0295 l1 1.000 0.0394 zd 1.250 0.0492 ze 1.250 0.0492
docid022063 rev 4 169/186 stm32f415xx, stm32f417xx package characteristics figure 85. lqfp176 recommended footprint 1. dimensions are expr essed in millimeters. ccc 0.080 0.0031 k0 7 0 7 1. values in inches are converted from mm and rounded to 4 decimal digits. table 95. lqfp176, 24 x 24 mm, 176-pin low-pr ofile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max 1t_fp_v1 133 132 1.2 0.3 0.5 89 88 1.2 44 45 21.8 26.7 1 176 26.7 21.8
package characteristics stm32f415xx, stm32f417xx 170/186 docid022063 rev 4 6.2 thermal characteristics the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: ? t a max is the maximum ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. table 96. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp64 - 10 10 mm / 0.5 mm pitch 46 c/w thermal resistance junction-ambient lqfp100 - 14 14 mm / 0.5 mm pitch 43 thermal resistance junction-ambient lqfp144 - 20 20 mm / 0.5 mm pitch 40 thermal resistance junction-ambient lqfp176 - 24 24 mm / 0.5 mm pitch 38 thermal resistance junction-ambient ufbga176 - 10 10 mm / 0.65 mm pitch 39 thermal resistance junction-ambient wlcsp90 - 0.400 mm pitch 38.1
docid022063 rev 4 171/186 stm32f415xx, stm32f417xx part numbering 7 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 97. ordering information scheme example: stm32 f 415 r e t 6 xxx device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose device subfamily 415 = stm32f41x, connectivity, cryptographic acceleration 417= stm32f41x, connectivity, camera interface, ethernet cryptographic acceleration, ethernet, pin count r = 64 pins o = 90 pins v = 100 pins z = 144 pins i = 176 pins flash memory size e = 512 kbytes of flash memory g = 1024 kbytes of flash memory package t = lqfp h = ufbga y = wlcsp temperature range 6 = industrial temperature range, ?40 to 85 c. 7 = industrial temperature range, ?40 to 105 c. options xxx = programmed parts tr = tape and reel
application block diagrams stm32f415xx, stm32f417xx 172/186 docid022063 rev 4 appendix a application block diagrams a.1 usb otg full speed (fs) interface solutions figure 86. usb controller configured as peripheral-only and used in full speed mode 1. external voltage regulator only needed when building a v bus powered device. 2. the same application can be developed using the otg hs in fs mode to achieve enhanced performance thanks to the large rx/tx fifo and to a dedicated dma controller. figure 87. usb controller configured as host-only and used in full speed mode 1. the current limiter is required only if the application has to support a v bus powered device. a basic power switch can be used if 5 v are available on the application board. 2. the same application can be developed using the otg hs in fs mode to achieve enhanced performance thanks to the large rx/tx fifo and to a dedicated dma controller. stm32f4xx 5v to v dd volatge regulator (1) v dd vbus dp v ss pa12/pb15 pa11//pb14 usb std-b connector dm osc_in osc_out ms19000v5 stm32f4xx v dd vbus dp v ss usb std-a connector dm gpio+irq gpio en overcurrent 5 v pwr osc_in osc_out ms19001v4 current limiter power switch (1) pa12/pb15 pa11//pb14
docid022063 rev 4 173/186 stm32f415xx, stm32f417xx application block diagrams figure 88. usb controller configured in dual mode and used in full speed mode 1. external voltage regulator only needed when building a v bus powered device. 2. the current limiter is required only if the application has to support a v bus powered device. a basic power switch can be used if 5 v are available on the application board. 3. the id pin is required in dual role only. 4. the same application can be developed using the otg hs in fs mode to achieve enhanced performance thanks to the large rx/tx fifo and to a dedicated dma controller. stm32f4xx v dd vbus dp v ss pa9/pb13 pa12/pb15 pa11/pb14 usb micro-ab connector dm gpio+irq gpio en overcurrent 5 v pwr 5 v to v dd voltage regulator (1) v dd id (3) pa10/pb12 osc_in osc_out ms19002v3 current limiter power switch (2)
application block diagrams stm32f415xx, stm32f417xx 174/186 docid022063 rev 4 a.2 usb otg high speed (h s) interface solutions figure 89. usb controller configured as peripheral, host, or dual-mode and used in high speed mode 1. it is possible to use mco1 or mco2 to save a crys tal. it is however not mandatory to clock the stm32f41x with a 24 or 26 mhz crystal when using usb hs. the above figure only shows an example of a possible connection. 2. the id pin is required in dual role only. dp stm32f4xx dm v bus v ss dm dp id (2) usb usb hs otg ctrl fs phy ulpi high speed otg phy ulpi_clk ulpi_d[7:0] ulpi_dir ulpi_stp ulpi_nxt not connected connector mco1 or mco2 24 or 26 mhz xt (1) pll xt1 xi ms19005v2
docid022063 rev 4 175/186 stm32f415xx, stm32f417xx application block diagrams a.3 ethernet interface solutions figure 90. mii mode using a 25 mhz crystal 1. f hclk must be greater than 25 mhz. 2. pulse per second when using ieee1588 ptp optional signal. figure 91. rmii with a 50 mhz oscillator 1. f hclk must be greater than 25 mhz. mcu ethernet mac 10/100 ethernet phy 10/100 pll hclk xt1 phy_clk 25 mhz mii_rx_clk mii_rxd[3:0] mii_rx_dv mii_rx_er mii_tx_clk mii_tx_en mii_txd[3:0] mii_crs mii_col mdio mdc hclk (1) pps_out (2) xtal 25 mhz stm32 osc tim2 timestamp comparator timer input trigger ieee1588 ptp mii = 15 pins mii + mdc = 17 pins ms19968v1 mco1/mco2 mcu ethernet mac 10/100 ethernet phy 10/100 pll hclk xt1 phy_clk 50 mhz rmii_rxd[1:0] rmii_crx_dv rmii_ref_clk rmii_tx_en rmii_txd[1:0] mdio mdc hclk (1) stm32 osc 50 mhz tim2 timestamp comparator timer input trigger ieee1588 ptp rmii = 7 pins rmii + mdc = 9 pins ms19969v1 /2 or /20 synchronous 2.5 or 25 mhz 50 mhz 50 mhz
application block diagrams stm32f415xx, stm32f417xx 176/186 docid022063 rev 4 figure 92. rmii with a 25 mhz crystal and phy with pll 1. f hclk must be greater than 25 mhz. 2. the 25 mhz (phy_clk) must be derived directly from the hse oscillator, before the pll block. mcu ethernet mac 10/100 ethernet phy 10/100 pll hclk xt1 phy_clk 25 mhz rmii_rxd[1:0] rmii_crx_dv rmii_ref_clk rmii_tx_en rmii_txd[1:0] mdio mdc hclk (1) stm32f tim2 timestamp comparator timer input trigger ieee1588 ptp rmii = 7 pins rmii + mdc = 9 pins ms19970v1 /2 or /20 synchronous 2.5 or 25 mhz 50 mhz xtal 25 mhz osc pll ref_clk mco1/mco2
docid022063 rev 4 177/186 stm32f415xx, stm32f417xx revision history 8 revision history table 98. document revision history date revision changes 15-sep-2011 1 initial release. 24-jan-2012 2 added wlcsp90 package on cover page. renamed usart4 and usart5 into uart4 and uart5, respectively. updated number of usb otg hs and fs in table 2: stm32f415xx and stm32f417xx: features and peripheral counts . updated figure 3: compatible board design between stm32f10xx/stm32f2xx/stm32f4xx for lqfp144 package and figure 4: compatible board design between stm32f2xx and stm32f4xx for lqfp176 and bga176 packages , and removed note 1 and 2. updated section 2.2.9: flexible stat ic memory controller (fsmc) . modified i/os used to reprogram the flash memory for can2 and usb otg fs in section 2.2.13: boot modes . updated note in section 2.2.14: power supply schemes . pdr_on no more available on lqfp100 package. updated section 2.2.16: voltage regulator . updated condition to obtain a minimum supply voltage of 1.7 v in the whole document. renamed usart4/5 to uart4/5 and added lin and irda feature for uart4 and uart5 in table 5: usart feature comparison . removed support of i2c for otg phy in section 2.2.30: universal serial bus on-the-go full-speed (otg_fs) . added table 6: legend/abbreviations used in the pinout table . table 7: stm32f41x pin and ball definitions : replaced v ss _3, v ss _4, and v ss _8 by v ss ; reformatted table 7: stm32f41x pin and ball definitions to better highlight i/o stru cture, and alternate functions versus additional functions; signal corresponding to lqfp100 pin 99 changed from pdr_on to v ss ; eventout added in the list of alternate functions for all i/os; a dc3_in8 added as alternate function for pf10; fsmc_cle and fsmc_ale added as alternate functions for pd11 and pd12, respectively; ph10 alternate function tim15_ch1_etr renamed tim5_ch1; updated pa4 and pa5 i/o structure to tta. removed otg_hs_scl, otg_hs_sda, otg_fs_intn in table 7: stm32f41x pin and ball definitions and table 9: alternate function mapping . changed tcm data ram to ccm data ram in figure 18: stm32f41x memory map . added i vdd and i vss maximum values in table 12: current characteristics . added note 1 related to f hclk , updated note 2 in table 14: general operating conditions , and added maximum power dissipation values. updated table 15: limitations depending on the operating power supply range .
revision history stm32f415xx, stm32f417xx 178/186 docid022063 rev 4 24-jan-2012 2 (continued) added v 12 in table 19: embedded reset and power control block characteristics . updated table 21: typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator disabled) and table 20: typical and maximum current consumption in run mode, code with data processing running from flash memory (art acce lerator enabled) or ram . added figure , figure 25 , figure 26 , and figure 27 . updated table 22: typical and maximum current consumption in sleep mode and removed note 1. updated table 23: typical and maximum current consumptions in stop mode and table 24: typical and maximum current consumptions in standby mode , table 25: typical and maximum current consumptions in vbat mode , and table 26: switching output i/o current consumption . section : on-chip peripheral current consumption : modified conditions, and updated table 27: peripheral current consumption and note 2 . changed f hse_ext to 50 mhz and t r(hse) /t f(hse) maximum value in table 29: high-speed external user clock characteristics . added c in(lse) in table 30: low-speed external user clock characteristics . updated maximum pll input clock frequency, removed related note, and deleted jitter for mco for rmii ethernet typical value in table 35: main pll characteristics . updated maximum plli2s input clock frequency and removed related note in table 36: plli2s (audio pll) characteristics . updated section : flash memory to specify that the devices are shipped to customers with the flash memory erased. updated table 38: flash memory characteristics , and added t me in table 39: flash memory programming . updated table 42: ems characteristics , and table 43: emi characteristics . updated table 56: i2s dynamic characteristics updated figure 46: ulpi timing diagram and table 62: ulpi timing . added t counter and t max_count in table 51: characteristics of timx connected to the apb1 domain and table 52: characteristics of timx connected to the apb2 domain . updated table 65: dynamic characteristics: ether net mac signals for rmii . removed usb-if certification in section : usb otg fs characteristics . table 98. document revision history (continued) date revision changes
docid022063 rev 4 179/186 stm32f415xx, stm32f417xx revision history 24-jan-2012 2 (continued) updated table 61: usb hs clock timing parameters updated table 67: adc characteristics . updated table 68: adc accuracy at fadc = 30 mhz . updated note 1 in table 74: dac characteristics . section 5.3.25: fsmc characteristics : updated table 75 to table 86 , changed c l value to 30 pf, and modified fsmc configuration for asynchronous timings and waveforms. updated figure 60: synchronous multiplexed psram write timings . updated table 96: package thermal characteristics . appendix a.1: usb otg full speed (fs) interface solutions : modified figure 86: usb controller configured as peripheral-only and used in full speed mode added note 2 , updated figure 87: usb controller configured as host-only and used in full speed mode and added note 2 , changed figure 88: usb controller configured in dual mode and used in full speed mode and added note 3 . appendix a.2: usb otg high speed (hs) interface solutions : removed figures usb otg hs device-only connection in fs mode and usb otg hs host-only connection in fs mode, and updated figure 89: usb controller configured as peri pheral, host, or dual-mode and used in high speed mode and added note 2 . added appendix a.3: ethernet interface solutions . table 98. document revision history (continued) date revision changes
revision history stm32f415xx, stm32f417xx 180/186 docid022063 rev 4 31-may-2012 3 updated figure 5: stm32f41x block diagram and figure 7: power supply supervisor interconnection with internal reset off added sdio, added notes related to fsmc and spi/i2s in table 2: stm32f415xx and stm32f417xx: features and peripheral counts . starting from silicon revision z, usb otg full-speed interface is now available for all stm32f415xx devices. added full information on wlcsp90 package together with corresponding part numbers. changed number of ahb buses to 3. modified available flash memory sizes in section 2.2.4: embedded flash memory . modified number of maskable interrupt channels in section 2.2.10: nested vectored interrupt controller (nvic) . updated case of regulator on/internal reset on, regulator on/internal reset off, and regulator off/internal reset on in section 2.2.16: voltage regulator . updated standby mode description in section 2.2.19: low-power modes . added note 1 below figure 16: stm32f41x ufbga176 ballout . added note 1 below figure 17: stm32f41x wlcsp90 ballout . updated table 7: stm32f41x pin and ball definitions . added table 8: fsmc pin definition . removed otg_hs_intn alternate function in table 7: stm32f41x pin and ball definitions and table 9: alternate function mapping . removed i2s2_ws on pb6/af5 in table 9: alternate function mapping . replaced jtrst by njtrst, removed eth_rmii _tx_clk, and modified i2s3ext_sd on pc11 in table 9: alternate function mapping . added table 10: stm32f41x register boundary addresses . updated figure 18: stm32f41x memory map . updated v dda and v ref+ decoupling capacitor in figure 21: power supply scheme . added power dissipation maximum value for wlcsp90 in ta ble 14 : general operating conditions . updated v por/pdr in table 19: embedded reset and power control block characteristics . updated notes in table 21: typical and maximum current consumption in run mode, code with data processing running from flash memory (art accelerator disabled) , table 20: typical and maximum current consumption in run mode, code with data processing running from flash memory (art acce lerator enabled) or ram , and ta ble 22 : typical and maximum current consumption in sleep mode . updated maximum current consumption at t a = 25 n table 23: typical and maximum current consumptions in stop mode . table 98. document revision history (continued) date revision changes
docid022063 rev 4 181/186 stm32f415xx, stm32f417xx revision history 31-may-2012 3 (continued) removed f hse_ext typical value in table 29: high-speed external user clock characteristics . updated table 31: hse 4-26 mhz oscillator characteristics and table 32: lse oscillator characteristics (flse = 32.768 khz) . added f pll48_out maximum value in table 35: main pll characteristics . modified equation 1 and 2 in section 5.3.11: pll spread spectrum clock generation (sscg) characteristics . updated table 38: flash memory characteristics , table 39: flash memory programming , and table 40: flash memory programming with vpp . updated section : output driving current . table 53: i2c characteristics : note 4 updated and applied to t h(sda) in fast mode, and removed note 4 related to t h(sda) minimum value. updated table 67: adc characteristics . updated note concerning adc accuracy vs. negative in jection current below table 68: adc accuracy at fadc = 30 mhz . added wlcsp90 thermal resistance in table 96: package thermal characteristics . updated table 90: wlcsp90 - 0.400 mm pitch wafer level chip size package mechanical data . updated figure 83: ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm, package outline and table 94: ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm mechanical data . added figure 85: lqfp176 recommended footprint . removed 256 and 768 kbyte flash memory density from table 97: ordering information scheme . table 98. document revision history (continued) date revision changes
revision history stm32f415xx, stm32f417xx 182/186 docid022063 rev 4 04-jun-2013 4 modified note 1 below table 2: stm32f415xx and stm32f417xx: features and peripheral counts . updated figure 4 title. updated note 3 below figure 21: power supply scheme . changed simplex mode into half-duplex mode in section 2.2.25: inter- integrated sound (i2s) . replaced dac1_out and dac2_out by dac_out1 and dac_out2, respectively. updated pin 36 signal in figure 15: stm32f41x lqfp176 pinout . changed pin number from f8 to d4 for pa13 pin in table 7: stm32f41x pin and ball definitions . replaced tim2_ch1/tim2_etr by tim2_ch1_etr for pa0 and pa5 pins in table 9: alternate function mapping . changed system memory into system memory + otp in figure 18: stm32f41x memory map . added note 1 below table 16: vcap_1/vcap_2 operating conditions . updated i dda description in table 74: dac characteristics . removed pa9/pb13 connection to vbus in figure 86: usb controller configured as peripheral-only and used in full speed mode and figure 87: usb controller configur ed as host-only and used in full speed mode . updated spi throughput on front page and section 2.2.24: serial peripheral interface (spi) updated operating voltages in table 2: stm32f415xx and stm32f417xx: features and peripheral counts updated note in section 2.2.14: power supply schemes updated section 2.2.15: power supply supervisor updated ?regulator on? paragraph in section 2.2.16: voltage regulator removed note in section 2.2.19: low-power modes corrected wrong reference manual in section 2.2.28: ethernet mac interface with dedicated dma and ieee 1588 support updated table 15: limitations depending on the operating power supply range updated table 24: typical and maximum current consumptions in standby mode updated table 25: typical and maximum current consumptions in vbat mode updated table 36: plli2s (audio pll) characteristics updated table 43: emi characteristics updated table 48: output voltage characteristics updated table 50: nrst pin characteristics updated table 55: spi dynamic characteristics updated table 56: i2s dynamic characteristics deleted table 59 updated table 62: ulpi timing updated figure 47: ethernet smi timing diagram table 98. document revision history (continued) date revision changes
docid022063 rev 4 183/186 stm32f415xx, stm32f417xx revision history 04-jun-2013 4 (continued) updated figure 83: ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm, package outline updated table 94: ufbga176+25 - ultra thin fine pitch ball grid array 10 10 0.6 mm mechanical data updated figure 5: stm32f41x block diagram updated section 2: description updated footnote (3) in table 2: stm32f415xx and stm32f417xx: features and peripheral counts updated figure 3: compatible board design between stm32f10xx/stm32f2xx/stm32f4xx for lqfp144 package updated figure 4: compatible board design between stm32f2xx and stm32f4xx for lqfp176 and bga176 packages updated section 2.2.14: power supply schemes updated section 2.2.15: power supply supervisor updated section 2.2.16: voltage regulator , including figures. updated table 14: general operating conditions , including footnote (2) . updated table 15: limitations depending on the operating power supply range , including footnote (3) . updated footnote (1) in table 67: adc characteristics . updated footnote (3) in table 68: adc accuracy at fadc = 30 mhz . updated footnote (1) in table 74: dac characteristics . updated figure 9: regulator off . updated figure 7: power supply supervisor interconnection with internal reset off . added section 2.2.17: regulator on/off and internal reset on/off availability . updated footnote (2) of figure 21: power supply scheme . replaced respectively ?i2s3s_ws" by "i2s3_ws?, ?i2s3s_ck? by ?i2s3_ck? and ?fsmc_bln1 ? by ?fsmc_nbl1? in table 9: alternate function mapping . added ?eventout? as alternate func tion ?af15? for pin pc13, pc14, pc15, ph0, ph1, pi8 in table 9: alternate function mapping replaced ?dcmi_12? by ?dcmi_d12? in table 7: stm32f41x pin and ball definitions . removed the following sentence from section : i2c interface characteristics : ?unless otherwise specified, the parameters given in table 53 are derived from tests performed under the ambient temperature, f pclk1 frequency and v dd supply voltage conditions summarized in table 14 .?. in table 7: stm32f41x pin and ball definitions on page 46 : ? for pin pc13, replaced ?rtc_a f1? by ?rtc_out, rtc_tamp1, rtc_ts? ? for pin pi8, replaced ?rtc_af2? by ?rtc_tamp1, rtc_tamp2, rtc_ts?. ? for pin pb15, added rtc_refin in alternate functions column. in table 9: alternate function mapping on page 61 , for port pb15, replaced ?rtc_50hz? by ?rtc_refin?. table 98. document revision history (continued) date revision changes
revision history stm32f415xx, stm32f417xx 184/186 docid022063 rev 4 04-jun-2013 4 (continued) updated figure 6: multi-ahb matrix . updated figure 7: power supply supervisor interconnection with internal reset off changed 1.2 v to v 12 in section : regulator off updated lqfp176 pin 48. updated section 1: introduction . updated section 2: description . updated operating voltage in table 2: stm32f415xx and stm32f417xx: features and peripheral counts . updated note 1 . updated section 2.2.15: power supply supervisor . updated section 2.2.16: voltage regulator . updated figure 9: regulator off . updated table 3: regulator on/off and internal reset on/off availability . updated section 2.2.19: low-power modes . updated section 2.2.20: vbat operation . updated section 2.2.22: inter-integrated circuit interface (i2c) . updated pin 48 in figure 15: stm32f41x lqfp176 pinout . updated table 6: legend/abbreviations used in the pinout table . updated table 7: stm32f41x pin and ball definitions . updated table 14: general operating conditions . updated table 15: limitations depending on the operating power supply range . updated section 5.3.7: wakeup time from low-power mode . updated table 33: hsi oscillator characteristics . updated section 5.3.15: i/o current injection characteristics . updated table 47: i/o static characteristics . updated table 50: nrst pin characteristics . updated table 53: i2c characteristics . updated figure 39: i2c bus ac waveforms and measurement circuit . updated section 5.3.19: commun ications interfaces . updated table 67: adc characteristics . added table 70: temperature s ensor calibration values . added table 73: internal reference voltage calibration values . updated section 5.3.25: fsmc characteristics . updated section 5.3.27: sd/sdio mmc ca rd host interface (sdio) characteristics . updated table 23: typical and maximum current consumptions in stop mode . updated section : spi interface characteristics included table 55 . updated section : i2s interface characteristics included ta ble 56 . updated table 64: dynamic characteristics: ehternet mac signals for smi . updated table 66: dynamic characterist ics: ethernet mac signals for mii . table 98. document revision history (continued) date revision changes
docid022063 rev 4 185/186 stm32f415xx, stm32f417xx revision history 04-jun-2013 4 (continued) updated table 64: dynamic characteristics: ehternet mac signals for smi . updated table 66: dynamic characterist ics: ethernet mac signals for mii . updated table 79: synchronous multiplexed nor/psram read timings . updated table 80: synchronous multiplexed psram write timings . updated table 81: synchronous non-mu ltiplexed nor/psram read timings . updated table 82: synchronous non-multiplexed psram write timings . updated section 5.3.26: camera interfac e (dcmi) timing specifications including table 87: dcmi characteristics and addition of figure 73: dcmi timing diagram . updated section 5.3.27: sd/sdio mmc ca rd host interface (sdio) characteristics including table 88 . updated chapter figure 9. table 98. document revision history (continued) date revision changes
stm32f415xx, stm32f417xx 186/186 docid022063 rev 4 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not authorized for use in weapons. nor are st products designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of STM32F417ZG

	To Download STM32F417ZG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .